}
tablegen("AMDGPUGenRegisterBank") {
- visibility = [ ":LLVMAMDGPUCodeGen" ]
+ visibility = [
+ ":LLVMAMDGPUCodeGen",
+ "Utils",
+ "//llvm/unittests/Target/AMDGPU:AMDGPUTests",
+ ]
args = [ "-gen-register-bank" ]
td_file = "AMDGPU.td"
}
output_name = "LLVMAMDGPUUtils"
public_deps = [ ":AMDGPUGenSearchableTables" ]
deps = [
+ # AMDGPUBaseInfo.cpp includes GCNSubtarget.h which after 490e348e679
+ # includes the generated AMDGPUGenRegisterBank.inc file :/
+ "../:AMDGPUGenRegisterBank",
"//llvm/lib/BinaryFormat",
"//llvm/lib/IR",
"//llvm/lib/MC",
deps = [
"//llvm/lib/Support",
"//llvm/lib/Target",
+
+ # AMDGPUBaseInfo.cpp includes GCNSubtarget.h which after 490e348e679
+ # includes the generated AMDGPUGenRegisterBank.inc file :/
+ "//llvm/lib/Target/AMDGPU/:AMDGPUGenRegisterBank",
"//llvm/lib/Target/AMDGPU:LLVMAMDGPUCodeGen",
"//llvm/lib/Target/AMDGPU/MCTargetDesc",
"//llvm/lib/Target/AMDGPU/TargetInfo",