include: sbi: Add TINFO debug trigger CSR

Add the missing TINFO debug trigger CSR.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index f20df761d9b3bdaecc28b91fd200ec56fd0db8bf..e74cc0df1c407e77716d2116c4864ffbe959c709 100644 (file)
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -686,6 +686,7 @@
 #define CSR_TDATA1                     0x7a1
 #define CSR_TDATA2                     0x7a2
 #define CSR_TDATA3                     0x7a3
+#define CSR_TINFO                      0x7a4
 
 /* Debug Mode Registers */
 #define CSR_DCSR                       0x7b0