info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
info->family == CHIP_RAVEN;
+ info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
+ info->chip_class <= GFX9;
+
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
/* Hardware bugs. */
bool has_gfx9_scissor_bug;
+ bool has_tc_compat_zrange_bug;
};
bool ac_query_gpu_info(int fd, void *dev_p,
uint32_t db_z_info = ds->db_z_info;
uint32_t db_z_info_reg;
- if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
+ if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
!radv_image_is_tc_compat_htile(image))
return;
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
- if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
+ if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
return;
uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
device->rad_info.family == CHIP_RENOIR;
}
- device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
-
device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
!(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
image->size = image->clear_value_offset + image->info.levels * 8;
if (radv_image_is_tc_compat_htile(image) &&
- device->physical_device->has_tc_compat_zrange_bug) {
+ device->physical_device->rad_info.has_tc_compat_zrange_bug) {
/* Metadata for the TC-compatible HTILE hardware bug which
* have to be fixed by updating ZRANGE_PRECISION when doing
* fast depth clears to 0.0f.
struct wsi_device wsi_device;
bool rbplus_allowed; /* if RB+ is allowed */
- bool has_tc_compat_zrange_bug;
bool out_of_order_rast_allowed;