MIPS: Define Config1 cache field shifts & sizes

These fields will be used from assembly code in a subsequent commit, and
defining the size & offset of each field makes that use easier.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0c74617..1f067cd 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -568,11 +568,23 @@
 #define MIPS_CONF1_PC          (_ULCAST_(1) <<  4)
 #define MIPS_CONF1_MD          (_ULCAST_(1) <<  5)
 #define MIPS_CONF1_C2          (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA_SHF      7
+#define MIPS_CONF1_DA_SZ       3
 #define MIPS_CONF1_DA          (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL_SHF      10
+#define MIPS_CONF1_DL_SZ       3
 #define MIPS_CONF1_DL          (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHF      13
+#define MIPS_CONF1_DS_SZ       3
 #define MIPS_CONF1_DS          (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHF      16
+#define MIPS_CONF1_IA_SZ       3
 #define MIPS_CONF1_IA          (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL_SHF      19
+#define MIPS_CONF1_IL_SZ       3
 #define MIPS_CONF1_IL          (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS_SHF      22
+#define MIPS_CONF1_IS_SZ       3
 #define MIPS_CONF1_IS          (_ULCAST_(7) << 22)
 #define MIPS_CONF1_TLBS_SHIFT   (25)
 #define MIPS_CONF1_TLBS_SIZE    (6)