Merge branch 'baserock/bjdooks/312-rc4/be/core-v3' of git://git.baserock.org/delta...

Conflicts:
	arch/arm/kernel/head.S

This series has been well tested and it would be great to get this
merged now.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --cc arch/arm/Kconfig
Simple merge

diff --cc arch/arm/common/mcpm_head.S
Simple merge

diff --cc arch/arm/include/asm/atomic.h
index 55ffc3b,6447a0b..134aa28
--- 1/arch/arm/include/asm/atomic.h
--- 2/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@@ -304,11 -299,10 +304,11 @@@ static inline void atomic64_add(u64 i, 
        u64 result;
        unsigned long tmp;
  
 +      prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic64_add\n"
  "1:   ldrexd  %0, %H0, [%3]\n"
- "     adds    %0, %0, %4\n"
- "     adc     %H0, %H0, %H4\n"
+ "     adds    %Q0, %Q0, %Q4\n"
+ "     adc     %R0, %R0, %R4\n"
  "     strexd  %1, %0, %H0, [%3]\n"
  "     teq     %1, #0\n"
  "     bne     1b"
@@@ -345,11 -339,10 +345,11 @@@ static inline void atomic64_sub(u64 i, 
        u64 result;
        unsigned long tmp;
  
 +      prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic64_sub\n"
  "1:   ldrexd  %0, %H0, [%3]\n"
- "     subs    %0, %0, %4\n"
- "     sbc     %H0, %H0, %H4\n"
+ "     subs    %Q0, %Q0, %Q4\n"
+ "     sbc     %R0, %R0, %R4\n"
  "     strexd  %1, %0, %H0, [%3]\n"
  "     teq     %1, #0\n"
  "     bne     1b"

diff --cc arch/arm/kernel/Makefile
Simple merge

diff --cc arch/arm/kernel/head.S
index 32402ba,a047acf..e46330f
--- 1/arch/arm/kernel/head.S
--- 2/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@@ -602,28 -586,26 +606,42 @@@ __fixup_a_pv_table
        b       2f
  1:    add     r7, r3
        ldrh    ip, [r7, #2]
 -      and     ip, 0x8f00
 -      orr     ip, r6  @ mask in offset bits 31-24
+ ARM_BE8(rev16 ip, ip)
 +      tst     ip, #0x4000
 +      and     ip, #0x8f00
 +      orrne   ip, r6  @ mask in offset bits 31-24
 +      orreq   ip, r0  @ mask in offset bits 7-0
+ ARM_BE8(rev16 ip, ip)
        strh    ip, [r7, #2]
-       ldrheq  ip, [r7]
-       biceq   ip, #0x20
-       orreq   ip, ip, r0, lsr #16
-       strheq  ip, [r7]
++      bne     2f
++      ldrh    ip, [r7]
++ARM_BE8(rev16 ip, ip)
++      bic     ip, #0x20
++      orr     ip, ip, r0, lsr #16
++ARM_BE8(rev16 ip, ip)
++      strh    ip, [r7]
  2:    cmp     r4, r5
        ldrcc   r7, [r4], #4    @ use branch for delay slot
        bcc     1b
        bx      lr
  #else
 +      moveq   r0, #0x400000   @ set bit 22, mov to mvn instruction
        b       2f
  1:    ldr     ip, [r7, r3]
 -      orr     ip, ip, r6, lsl#24
+ #ifdef CONFIG_CPU_ENDIAN_BE8
+       @ in BE8, we load data in BE, but instructions still in LE
+       bic     ip, ip, #0xff000000
++      tst     ip, #0x000f0000 @ check the rotation field
++      orrne   ip, ip, r6, lsl #24 @ mask in offset bits 31-24
++      biceq   ip, ip, #0x00004000 @ clear bit 22
++      orreq   ip, ip, r0, lsl #24 @ mask in offset bits 7-0
+ #else
        bic     ip, ip, #0x000000ff
 -      orr     ip, ip, r6      @ mask in offset bits 31-24
 +      tst     ip, #0xf00      @ check the rotation field
 +      orrne   ip, ip, r6      @ mask in offset bits 31-24
 +      biceq   ip, ip, #0x400000       @ clear bit 22
 +      orreq   ip, ip, r0      @ mask in offset bits 7-0
+ #endif
        str     ip, [r7, r3]
  2:    cmp     r4, r5
        ldrcc   r7, [r4], #4    @ use branch for delay slot

diff --cc arch/arm/kernel/sleep.S
Simple merge