[CSKY] support select instruction in floating type

In FPUv3, there is fsel.32/64 instruction to select float/double type data.
In FPUv2, split block and use branch and move instruction to select float/double type data.

diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index e7e7739..012de34 100644 (file)
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -1021,6 +1021,12 @@ CSKYTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   switch (MI.getOpcode()) {
   default:
     llvm_unreachable("Unexpected instr type to insert");
+  case CSKY::FSELS:
+  case CSKY::FSELD:
+    if (Subtarget.hasE2())
+      return emitSelectPseudo(MI, BB, CSKY::BT32);
+    else
+      return emitSelectPseudo(MI, BB, CSKY::BT16);
   case CSKY::ISEL32:
     return emitSelectPseudo(MI, BB, CSKY::BT32);
   case CSKY::ISEL16:

diff --git a/llvm/test/CodeGen/CSKY/fpu/select.ll b/llvm/test/CodeGen/CSKY/fpu/select.ll
new file mode 100644 (file)
index 0000000..81216a1
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/select.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv3_sf,+fpuv3_df -float-abi=hard | FileCheck %s --check-prefix=CHECK-DF3
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
+
+define float @selectRR_eq_float(i1 %x, float %n, float %m) {
+; CHECK-LABEL: selectRR_eq_float:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    btsti32 a0, 0
+; CHECK-NEXT:    bt32 .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    fmovs vr1, vr0
+; CHECK-NEXT:  .LBB0_2: # %entry
+; CHECK-NEXT:    fmovs vr0, vr1
+; CHECK-NEXT:    rts16
+;
+; CHECK-DF3-LABEL: selectRR_eq_float:
+; CHECK-DF3:       # %bb.0: # %entry
+; CHECK-DF3-NEXT:    btsti32 a0, 0
+; CHECK-DF3-NEXT:    fsel.32 vr0, vr1, vr0
+; CHECK-DF3-NEXT:    rts16
+;
+; GENERIC-LABEL: selectRR_eq_float:
+; GENERIC:       # %bb.0: # %entry
+; GENERIC-NEXT:    .cfi_def_cfa_offset 0
+; GENERIC-NEXT:    subi16 sp, sp, 4
+; GENERIC-NEXT:    .cfi_def_cfa_offset 4
+; GENERIC-NEXT:    btsti16 a0, 0
+; GENERIC-NEXT:    bt16 .LBB0_2
+; GENERIC-NEXT:  # %bb.1: # %entry
+; GENERIC-NEXT:    fmovs vr1, vr0
+; GENERIC-NEXT:  .LBB0_2: # %entry
+; GENERIC-NEXT:    fmovs vr0, vr1
+; GENERIC-NEXT:    addi16 sp, sp, 4
+; GENERIC-NEXT:    rts16
+entry:
+  %ret = select i1 %x, float %m, float %n
+  ret float %ret
+}
+
+define double @selectRR_eq_double(i1 %x, double %n, double %m) {
+; CHECK-LABEL: selectRR_eq_double:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    btsti32 a0, 0
+; CHECK-NEXT:    bt32 .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    fmovd vr1, vr0
+; CHECK-NEXT:  .LBB1_2: # %entry
+; CHECK-NEXT:    fmovd vr0, vr1
+; CHECK-NEXT:    rts16
+;
+; CHECK-DF3-LABEL: selectRR_eq_double:
+; CHECK-DF3:       # %bb.0: # %entry
+; CHECK-DF3-NEXT:    btsti32 a0, 0
+; CHECK-DF3-NEXT:    fsel.64 vr0, vr1, vr0
+; CHECK-DF3-NEXT:    rts16
+;
+; GENERIC-LABEL: selectRR_eq_double:
+; GENERIC:       # %bb.0: # %entry
+; GENERIC-NEXT:    .cfi_def_cfa_offset 0
+; GENERIC-NEXT:    subi16 sp, sp, 4
+; GENERIC-NEXT:    .cfi_def_cfa_offset 4
+; GENERIC-NEXT:    btsti16 a0, 0
+; GENERIC-NEXT:    bt16 .LBB1_2
+; GENERIC-NEXT:  # %bb.1: # %entry
+; GENERIC-NEXT:    fmovd vr1, vr0
+; GENERIC-NEXT:  .LBB1_2: # %entry
+; GENERIC-NEXT:    fmovd vr0, vr1
+; GENERIC-NEXT:    addi16 sp, sp, 4
+; GENERIC-NEXT:    rts16
+entry:
+  %ret = select i1 %x, double %m, double %n
+  ret double %ret
+}
+