<!-- not actually encoded, but used for IR -->
<immediate name="sr_count" size="4" pseudo="true"/>
<immediate name="sr_count_2" size="4" pseudo="true"/>
+ <mod name="register_format" size="4" pseudo="true">
+ <opt>f16</opt>
+ <opt>f32</opt>
+ <opt>s32</opt>
+ <opt>u32</opt>
+ <opt>s16</opt>
+ <opt>u16</opt>
+ <opt>f64</opt>
+ <opt>i64</opt>
+ <opt>auto</opt>
+ </mod>
</ins>
<ins name="+BRANCH.f16" mask="0xf8000" exact="0x68000" last="true" dests="0">
unsigned sr_count_2 = (size_2 <= 16) ? 2 : 4;
const struct panfrost_compile_inputs *inputs = b->shader->inputs;
uint64_t blend_desc = inputs->blend.bifrost_blend_desc;
+ enum bi_register_format regfmt = bi_reg_fmt_for_nir(T);
if (inputs->is_blend && inputs->blend.nr_samples > 1) {
/* Conversion descriptor comes from the compile inputs, pixel
bi_register(60),
bi_imm_u32(blend_desc & 0xffffffff),
bi_imm_u32(blend_desc >> 32),
- bi_null(), sr_count, 0);
+ bi_null(), regfmt, sr_count, 0);
} else {
/* Blend descriptor comes from the FAU RAM. By convention, the
* return address is stored in r48 and will be used by the
bi_register(60),
bi_fau(BIR_FAU_BLEND_0 + rt, false),
bi_fau(BIR_FAU_BLEND_0 + rt, true),
- rgba2, sr_count, sr_count_2);
+ rgba2, regfmt, sr_count, sr_count_2);
}
assert(rt < 8);
TEST_F(SchedulerPredicates, BLEND)
{
- bi_instr *blend = bi_blend_to(b, TMP(), TMP(), TMP(), TMP(), TMP(), TMP(), 4, 4);
+ bi_instr *blend = bi_blend_to(b, TMP(), TMP(), TMP(), TMP(), TMP(), TMP(),
+ BI_REGISTER_FORMAT_F32, 4, 4);
ASSERT_FALSE(bi_can_fma(blend));
ASSERT_TRUE(bi_can_add(blend));
ASSERT_TRUE(bi_must_message(blend));