gas/

2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (match_template): Don't explicitly check
	suffix for crc32 in Intel mode.
	(process_suffix): Issue an error for crc32 if the operand size
	is ambiguous.

gas/testsuite/

2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/crc32-intel.d: Updated.
	* gas/i386/crc32.d: Likewise.
	* gas/i386/sse4_2.d: Likewise.
	* gas/i386/x86-64-crc32-intel.d: Likewise.
	* gas/i386/x86-64-crc32.d: Likewise.
	* gas/i386/x86-64-sse4_2.d: Likewise.

	* gas/i386/crc32.s: Remove crc32 instructions with ambiguous
	operand size and suffix in crc32 instructions in Intel mode.
	* gas/i386/x86-64-crc32.s: Likewise.

	* gas/i386/sse4_2.s: Remove crc32 instructions with ambiguous
	operand size.
	* gas/i386/x86-64-sse4_2.s: Likewise.

	* gas/i386/i386.exp: Run inval-crc32 and x86-64-inval-crc32.

	* gas/i386/inval-crc32.l: New.
	* gas/i386/inval-crc32.s: Likewise.
	* gas/i386/x86-64-inval-crc32.l: Likewise.
	* gas/i386/x86-64-inval-crc32.s: Likewise.

opcodes/

2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.

	* i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
	type for crc32.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3a38e5e..e77aa6c 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (match_template): Don't explicitly check
+       suffix for crc32 in Intel mode.
+       (process_suffix): Issue an error for crc32 if the operand size
+       is ambiguous.
+
 2007-05-03  Vincent Riviere  <vincent.riviere@freesbee.fr>
            Nick Clifton  <nickc@redhat.com>
 

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index e091322..b96871f 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2557,11 +2557,9 @@ match_template (void)
       if (i.operands != t->operands)
        continue;
 
-      /* Check the suffix, except for some instructions in intel mode.
-        We do want to check suffix for crc32 even in intel mode.  */
+      /* Check the suffix, except for some instructions in intel mode.  */
       if ((t->opcode_modifier & suffix_check)
          && !(intel_syntax
-              && t->base_opcode != 0xf20f38f1
               && (t->opcode_modifier & IgnoreSize)))
        continue;
 
@@ -2848,12 +2846,24 @@ process_suffix (void)
                            LONG_MNEM_SUFFIX);
            }
          else if (i.tm.base_opcode == 0xf20f38f0)
-           i.suffix = BYTE_MNEM_SUFFIX;
+           {
+             if ((i.types[0] & Reg8))
+               i.suffix = BYTE_MNEM_SUFFIX;
+           }
 
          if (!i.suffix)
            {
              int op;
 
+             if (i.tm.base_opcode == 0xf20f38f1
+                 || i.tm.base_opcode == 0xf20f38f0)
+               {
+                 /* We have to know the operand size for crc32.  */
+                 as_bad (_("ambiguous memory operand size for `%s`"),
+                         i.tm.name);
+                 return 0;
+               }
+
              for (op = i.operands; --op >= 0;)
                if ((i.types[op] & Reg)
                    && !(i.tm.operand_types[op] & InOutPortReg))

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0148bfb..724400c 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,27 @@
+2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * gas/i386/crc32-intel.d: Updated.
+       * gas/i386/crc32.d: Likewise.
+       * gas/i386/sse4_2.d: Likewise.
+       * gas/i386/x86-64-crc32-intel.d: Likewise.
+       * gas/i386/x86-64-crc32.d: Likewise.
+       * gas/i386/x86-64-sse4_2.d: Likewise.
+
+       * gas/i386/crc32.s: Remove crc32 instructions with ambiguous
+       operand size and suffix in crc32 instructions in Intel mode.
+       * gas/i386/x86-64-crc32.s: Likewise.
+
+       * gas/i386/sse4_2.s: Remove crc32 instructions with ambiguous
+       operand size.
+       * gas/i386/x86-64-sse4_2.s: Likewise.
+
+       * gas/i386/i386.exp: Run inval-crc32 and x86-64-inval-crc32.
+
+       * gas/i386/inval-crc32.l: New.
+       * gas/i386/inval-crc32.s: Likewise.
+       * gas/i386/x86-64-inval-crc32.l: Likewise.
+       * gas/i386/x86-64-inval-crc32.s: Likewise.
+
 2007-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gas/i386/crc32-intel.d: New file.

diff --git a/gas/testsuite/gas/i386/crc32-intel.d b/gas/testsuite/gas/i386/crc32-intel.d
index 0a6a643..705f6b8 100644 (file)
--- a/gas/testsuite/gas/i386/crc32-intel.d
+++ b/gas/testsuite/gas/i386/crc32-intel.d
@@ -7,26 +7,19 @@
 Disassembly of section .text:
 
 0+ <foo>:
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b eax,BYTE PTR \[esi\]
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w eax,WORD PTR \[esi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[esi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[esi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b eax,BYTE PTR \[esi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b eax,BYTE PTR \[esi\]
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w eax,WORD PTR \[esi\]
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w eax,WORD PTR \[esi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[esi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[esi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
+[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32  eax,BYTE PTR \[esi\]
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32  eax,WORD PTR \[esi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32  eax,DWORD PTR \[esi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32  eax,al
+[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32  eax,al
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32  eax,ax
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32  eax,ax
+[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32  eax,eax
+[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32  eax,eax
+[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32  eax,BYTE PTR \[esi\]
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32  eax,WORD PTR \[esi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32  eax,DWORD PTR \[esi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32  eax,al
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32  eax,ax
+[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32  eax,eax
 #pass

diff --git a/gas/testsuite/gas/i386/crc32.d b/gas/testsuite/gas/i386/crc32.d
index 9dbfdca..a398a75 100644 (file)
--- a/gas/testsuite/gas/i386/crc32.d
+++ b/gas/testsuite/gas/i386/crc32.d
@@ -9,7 +9,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b \(%esi\),%eax
 [      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%esi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%esi\),%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%esi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
 [      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
@@ -17,15 +16,9 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b \(%esi\),%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b \(%esi\),%eax
 [      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%esi\),%eax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%esi\),%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%esi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%esi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
 [      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
 #pass

diff --git a/gas/testsuite/gas/i386/crc32.s b/gas/testsuite/gas/i386/crc32.s
index 711fe8a..edcfe1c 100644 (file)
--- a/gas/testsuite/gas/i386/crc32.s
+++ b/gas/testsuite/gas/i386/crc32.s
@@ -6,7 +6,6 @@ foo:
 crc32b (%esi), %eax
 crc32w (%esi), %eax
 crc32l (%esi), %eax
-crc32 (%esi), %eax
 crc32  %al, %eax
 crc32b  %al, %eax
 crc32  %ax, %eax
@@ -15,17 +14,11 @@ crc32  %eax, %eax
 crc32l  %eax, %eax
 
 .intel_syntax noprefix
-crc32b  eax,byte ptr [esi]
 crc32  eax,byte ptr [esi]
-crc32w  eax, word ptr [esi]
 crc32  eax, word ptr [esi]
-crc32d  eax,dword ptr [esi]
 crc32  eax,dword ptr [esi]
 crc32  eax,al
-crc32b  eax,al
 crc32  eax, ax
-crc32w  eax, ax
 crc32  eax,eax
-crc32d  eax,eax
 
 .p2align 4,0

diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index c65a6fc..e0702f5 100644 (file)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -90,6 +90,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "sse4_2"
     run_dump_test "crc32"
     run_dump_test "crc32-intel"
+    run_list_test "inval-crc32" "-al"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -181,6 +182,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-sse4_2"
     run_dump_test "x86-64-crc32"
     run_dump_test "x86-64-crc32-intel"
+    run_list_test "x86-64-inval-crc32" "-al"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]

diff --git a/gas/testsuite/gas/i386/inval-crc32.l b/gas/testsuite/gas/i386/inval-crc32.l
new file mode 100644 (file)
index 0000000..14f908d
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-crc32.l
@@ -0,0 +1,43 @@
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+GAS LISTING .*
+
+
+[      ]*1[    ]+\# Check illegal crc32 in SSE4\.2
+[      ]*2[    ]+
+[      ]*3[    ]+\.text
+[      ]*4[    ]+foo:
+[      ]*5[    ]+
+[      ]*6[    ]+crc32b \(%esi\), %al
+[      ]*7[    ]+crc32w \(%esi\), %ax
+[      ]*8[    ]+crc32 \(%esi\), %al
+[      ]*9[    ]+crc32 \(%esi\), %ax
+[      ]*10[   ]+crc32 \(%esi\), %eax
+[      ]*11[   ]+crc32  %al, %al
+[      ]*12[   ]+crc32b  %al, %al
+[      ]*13[   ]+crc32  %ax, %ax
+[      ]*14[   ]+crc32w  %ax, %ax
+[      ]*15[   ]+
+[      ]*16[   ]+\.intel_syntax noprefix
+[      ]*17[   ]+crc32  al,byte ptr \[esi\]
+[      ]*18[   ]+crc32  ax, word ptr \[esi\]
+[      ]*19[   ]+crc32  al, \[esi\]
+[      ]*20[   ]+crc32  ax, \[esi\]
+[      ]*21[   ]+crc32  eax, \[esi\]
+[      ]*22[   ]+crc32  al,al
+[      ]*23[   ]+crc32  ax, ax

diff --git a/gas/testsuite/gas/i386/inval-crc32.s b/gas/testsuite/gas/i386/inval-crc32.s
new file mode 100644 (file)
index 0000000..5232fb0
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-crc32.s
@@ -0,0 +1,23 @@
+# Check illegal crc32 in SSE4.2
+
+       .text
+foo:
+
+crc32b (%esi), %al
+crc32w (%esi), %ax
+crc32 (%esi), %al
+crc32 (%esi), %ax
+crc32 (%esi), %eax
+crc32  %al, %al
+crc32b  %al, %al
+crc32  %ax, %ax
+crc32w  %ax, %ax
+
+.intel_syntax noprefix
+crc32  al,byte ptr [esi]
+crc32  ax, word ptr [esi]
+crc32  al, [esi]
+crc32  ax, [esi]
+crc32  eax, [esi]
+crc32  al,al
+crc32  ax, ax

diff --git a/gas/testsuite/gas/i386/sse4_2.d b/gas/testsuite/gas/i386/sse4_2.d
index e6468b3..b889769 100644 (file)
--- a/gas/testsuite/gas/i386/sse4_2.d
+++ b/gas/testsuite/gas/i386/sse4_2.d
@@ -6,7 +6,6 @@
 Disassembly of section .text:
 
 0+000 <foo>:
-[      ]*[0-9a-f]+:    f2 0f 38 f1 19          crc32l \(%ecx\),%ebx
 [      ]*[0-9a-f]+:    f2 0f 38 f0 d9          crc32b %cl,%ebx
 [      ]*[0-9a-f]+:    66 f2 0f 38 f1 d9       crc32w %cx,%ebx
 [      ]*[0-9a-f]+:    f2 0f 38 f1 d9          crc32l %ecx,%ebx

diff --git a/gas/testsuite/gas/i386/sse4_2.s b/gas/testsuite/gas/i386/sse4_2.s
index 584757c..a6c2e46 100644 (file)
--- a/gas/testsuite/gas/i386/sse4_2.s
+++ b/gas/testsuite/gas/i386/sse4_2.s
@@ -2,7 +2,6 @@
 
        .text
 foo:
-       crc32           (%ecx),%ebx
        crc32           %cl,%ebx
        crc32           %cx,%ebx
        crc32           %ecx,%ebx

diff --git a/gas/testsuite/gas/i386/x86-64-crc32-intel.d b/gas/testsuite/gas/i386/x86-64-crc32-intel.d
index 53c63d1..24bd66d 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-crc32-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-crc32-intel.d
@@ -7,40 +7,29 @@
 Disassembly of section .text:
 
 0+ <foo>:
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b eax,BYTE PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32b rax,BYTE PTR \[rsi\]
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w eax,WORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q rax,QWORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b rax,al
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b rax,al
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q rax,rax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q rax,rax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32b rax,BYTE PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32b rax,BYTE PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b eax,BYTE PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b eax,BYTE PTR \[rsi\]
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w eax,WORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w eax,WORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32d eax,DWORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q rax,QWORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q rax,QWORD PTR \[rsi\]
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b eax,al
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b rax,al
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b rax,al
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w eax,ax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32d eax,eax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q rax,rax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q rax,rax
+[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32  eax,BYTE PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32  rax,BYTE PTR \[rsi\]
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32  eax,WORD PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32  eax,DWORD PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32  rax,QWORD PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32  eax,al
+[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32  eax,al
+[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32  rax,al
+[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32  rax,al
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32  eax,ax
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32  eax,ax
+[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32  eax,eax
+[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32  eax,eax
+[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32  rax,rax
+[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32  rax,rax
+[      ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32  rax,BYTE PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32  eax,BYTE PTR \[rsi\]
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32  eax,WORD PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32  eax,DWORD PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32  rax,QWORD PTR \[rsi\]
+[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32  eax,al
+[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32  rax,al
+[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32  eax,ax
+[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32  eax,eax
+[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32  rax,rax
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-crc32.d b/gas/testsuite/gas/i386/x86-64-crc32.d
index e6a955a..1a33fac 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-crc32.d
+++ b/gas/testsuite/gas/i386/x86-64-crc32.d
@@ -11,7 +11,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%rsi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%rsi\),%eax
 [      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q \(%rsi\),%rax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%rsi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
 [      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b %al,%rax
@@ -23,23 +22,13 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q %rax,%rax
 [      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q %rax,%rax
 [      ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32b \(%rsi\),%rax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32b \(%rsi\),%rax
-[      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b \(%rsi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b \(%rsi\),%eax
 [      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%rsi\),%eax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%rsi\),%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%rsi\),%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%rsi\),%eax
 [      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q \(%rsi\),%rax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q \(%rsi\),%rax
 [      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b %al,%rax
 [      ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b %al,%rax
 [      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
-[      ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
 [      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
-[      ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
-[      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q %rax,%rax
 [      ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q %rax,%rax
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-crc32.s b/gas/testsuite/gas/i386/x86-64-crc32.s
index 069f7ba..7ebe894 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-crc32.s
+++ b/gas/testsuite/gas/i386/x86-64-crc32.s
@@ -1,4 +1,4 @@
-# crc32 in SSE4.2
+# Check 64bit crc32 in SSE4.2
 
        .text
 foo:
@@ -8,7 +8,6 @@ crc32b (%rsi), %rax
 crc32w (%rsi), %eax
 crc32l (%rsi), %eax
 crc32q (%rsi), %rax
-crc32 (%rsi), %eax
 crc32  %al, %eax
 crc32b  %al, %eax
 crc32  %al, %rax
@@ -21,25 +20,15 @@ crc32  %rax, %rax
 crc32q  %rax, %rax
 
 .intel_syntax noprefix
-crc32b  rax,byte ptr [rsi]
 crc32  rax,byte ptr [rsi]
-crc32b  eax,byte ptr [rsi]
 crc32  eax,byte ptr [rsi]
-crc32w  eax, word ptr [rsi]
 crc32  eax, word ptr [rsi]
-crc32d  eax,dword ptr [rsi]
 crc32  eax,dword ptr [rsi]
-crc32q  rax,qword ptr [rsi]
 crc32  rax,qword ptr [rsi]
 crc32  eax,al
-crc32b  eax,al
 crc32  rax,al
-crc32b  rax,al
 crc32  eax, ax
-crc32w  eax, ax
 crc32  eax,eax
-crc32d  eax,eax
 crc32  rax,rax
-crc32q  rax,rax
 
 .p2align 4,0

diff --git a/gas/testsuite/gas/i386/x86-64-inval-crc32.l b/gas/testsuite/gas/i386/x86-64-inval-crc32.l
new file mode 100644 (file)
index 0000000..b4a8eaa
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-crc32.l
@@ -0,0 +1,65 @@
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+.*:15: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+GAS LISTING .*
+
+
+[      ]*1[    ]+\# Check illegal 64bit crc32 in SSE4\.2
+[      ]*2[    ]+
+[      ]*3[    ]+\.text
+[      ]*4[    ]+foo:
+[      ]*5[    ]+
+[      ]*6[    ]+crc32b \(%rsi\), %al
+[      ]*7[    ]+crc32w \(%rsi\), %ax
+[      ]*8[    ]+crc32 \(%rsi\), %al
+[      ]*9[    ]+crc32 \(%rsi\), %ax
+[      ]*10[   ]+crc32 \(%rsi\), %eax
+[      ]*11[   ]+crc32 \(%rsi\), %rax
+[      ]*12[   ]+crc32  %al, %al
+[      ]*13[   ]+crc32b  %al, %al
+[      ]*14[   ]+crc32  %ax, %ax
+[      ]*15[   ]+crc32w  %ax, %ax
+[      ]*16[   ]+crc32  %rax, %eax
+[      ]*17[   ]+crc32  %eax, %rax
+[      ]*18[   ]+crc32l  %rax, %eax
+[      ]*19[   ]+crc32l  %eax, %rax
+[      ]*20[   ]+crc32q  %eax, %rax
+[      ]*21[   ]+crc32q  %rax, %eax
+[      ]*22[   ]+
+[      ]*23[   ]+\.intel_syntax noprefix
+[      ]*24[   ]+crc32  al,byte ptr \[rsi\]
+[      ]*25[   ]+crc32  ax, word ptr \[rsi\]
+[      ]*26[   ]+crc32  rax,word ptr \[rsi\]
+[      ]*27[   ]+crc32  rax,dword ptr \[rsi\]
+[      ]*28[   ]+crc32  al,\[rsi\]
+[      ]*29[   ]+crc32  ax,\[rsi\]
+[      ]*30[   ]+crc32  eax,\[rsi\]
+[      ]*31[   ]+crc32  rax,\[rsi\]
+[      ]*32[   ]+crc32  al,al
+[      ]*33[   ]+crc32  ax, ax
+[      ]*34[   ]+crc32  rax,eax

diff --git a/gas/testsuite/gas/i386/x86-64-inval-crc32.s b/gas/testsuite/gas/i386/x86-64-inval-crc32.s
new file mode 100644 (file)
index 0000000..7740811
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-crc32.s
@@ -0,0 +1,34 @@
+# Check illegal 64bit crc32 in SSE4.2
+
+       .text
+foo:
+
+crc32b (%rsi), %al
+crc32w (%rsi), %ax
+crc32 (%rsi), %al
+crc32 (%rsi), %ax
+crc32 (%rsi), %eax
+crc32 (%rsi), %rax
+crc32  %al, %al
+crc32b  %al, %al
+crc32  %ax, %ax
+crc32w  %ax, %ax
+crc32  %rax, %eax
+crc32  %eax, %rax
+crc32l  %rax, %eax
+crc32l  %eax, %rax
+crc32q  %eax, %rax
+crc32q  %rax, %eax
+
+.intel_syntax noprefix
+crc32  al,byte ptr [rsi]
+crc32  ax, word ptr [rsi]
+crc32  rax,word ptr [rsi]
+crc32  rax,dword ptr [rsi]
+crc32  al,[rsi]
+crc32  ax,[rsi]
+crc32  eax,[rsi]
+crc32  rax,[rsi]
+crc32  al,al
+crc32  ax, ax
+crc32  rax,eax

diff --git a/gas/testsuite/gas/i386/x86-64-sse4_2.d b/gas/testsuite/gas/i386/x86-64-sse4_2.d
index b541f74..379dbb5 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse4_2.d
+++ b/gas/testsuite/gas/i386/x86-64-sse4_2.d
@@ -6,8 +6,6 @@
 Disassembly of section .text:
 
 0+000 <foo>:
-[      ]*[0-9a-f]+:    f2 0f 38 f1 19          crc32l \(%rcx\),%ebx
-[      ]*[0-9a-f]+:    f2 48 0f 38 f1 19       crc32q \(%rcx\),%rbx
 [      ]*[0-9a-f]+:    f2 0f 38 f0 d9          crc32b %cl,%ebx
 [      ]*[0-9a-f]+:    f2 48 0f 38 f0 d9       crc32b %cl,%rbx
 [      ]*[0-9a-f]+:    66 f2 0f 38 f1 d9       crc32w %cx,%ebx

diff --git a/gas/testsuite/gas/i386/x86-64-sse4_2.s b/gas/testsuite/gas/i386/x86-64-sse4_2.s
index fdc7491..9d59b10 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse4_2.s
+++ b/gas/testsuite/gas/i386/x86-64-sse4_2.s
@@ -2,8 +2,6 @@
 
        .text
 foo:
-       crc32           (%rcx),%ebx
-       crc32           (%rcx),%rbx
        crc32           %cl,%ebx
        crc32           %cl,%rbx
        crc32           %cx,%ebx

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index afdba13..60eed94 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.
+
+       * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
+       type for crc32.
+
 2007-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 2f26e06..b74a51e 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -6384,14 +6384,20 @@ CRC32_Fixup (int bytemode, int sizeflag)
   switch (bytemode)
     {
     case b_mode:
+      if (intel_syntax)
+       break;
+
       *p++ = 'b';
       break;
     case v_mode:
+      if (intel_syntax)
+       break;
+
       USED_REX (REX_W);
       if (rex & REX_W)
        *p++ = 'q';
       else if (sizeflag & DFLAG)
-       *p++ = intel_syntax ? 'd' : 'l';
+       *p++ = 'l';
       else
        *p++ = 'w';
       used_prefixes |= (prefixes & PREFIX_DATA);

diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c
index e03152c..b0f4884 100644 (file)
--- a/opcodes/i386-opc.c
+++ b/opcodes/i386-opc.c
@@ -1444,10 +1444,10 @@ const template i386_optab[] =
 {"pcmpistrm", 3,  0x660f3a62,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm,     { Imm8, RegXMM|LLongMem, RegXMM } },
 /* We put non-8bit version before 8bit so that crc32 with memory operand
    defaults to non-8bit.  */
-{"crc32",     2,  0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm,               { WordReg|WordMem, Reg32, 0 } },
-{"crc32",     2,  0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|IgnoreSize|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } },
+{"crc32",     2,  0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm,               { Reg16|Reg32|ShortMem|LongMem, Reg32, 0 } },
+{"crc32",     2,  0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|Modrm|Rex64,    { Reg64|LLongMem, Reg64, 0 } },
 {"crc32",     2,  0xf20f38f0,X, CpuSSE4_2, b_Suf|Modrm,                        { Reg8|ByteMem, Reg32, 0 } },
-{"crc32",     2,  0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|IgnoreSize|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0 } },
+{"crc32",     2,  0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|Modrm|Rex64,    { Reg8|ByteMem, Reg64, 0 } },
 
 /* AMD 3DNow! instructions.  */