MAINTAINERS: add polarfire rng, pci and clock drivers
authorConor Dooley <conor.dooley@microchip.com>
Thu, 7 Jul 2022 14:20:42 +0000 (15:20 +0100)
committerArnd Bergmann <arnd@arndb.de>
Fri, 8 Jul 2022 07:09:46 +0000 (09:09 +0200)
Hardware random, PCI and clock drivers for the PolarFire SoC have been
upstreamed but are not covered by the MAINTAINERS entry, so add them.
Daire is the author of the clock & PCI drivers, so add him as a
maintainer in place of Lewis.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220707142041.4096246-1-conor.dooley@microchip.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
MAINTAINERS

index e20124d..7a3eab7 100644 (file)
@@ -17202,12 +17202,15 @@ N:    riscv
 K:     riscv
 
 RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
-M:     Lewis Hanly <lewis.hanly@microchip.com>
 M:     Conor Dooley <conor.dooley@microchip.com>
+M:     Daire McNamara <daire.mcnamara@microchip.com>
 L:     linux-riscv@lists.infradead.org
 S:     Supported
 F:     arch/riscv/boot/dts/microchip/
+F:     drivers/char/hw_random/mpfs-rng.c
+F:     drivers/clk/microchip/clk-mpfs.c
 F:     drivers/mailbox/mailbox-mpfs.c
+F:     drivers/pci/controller/pcie-microchip-host.c
 F:     drivers/soc/microchip/
 F:     include/soc/microchip/mpfs.h