lcd: optimize tcon_pll for tl1 [1/1]

PD#SWPL-3493

Problem:
tl1 can imporve tcon_pll performance

Solution:
1.update tcon_pll cntl2 register
2.extend ss_level to 12 level

Verify:
x301

Change-Id: Id10479196529083d2bf5048695a682793a4945ca
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
index d6db1cf..8778249 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
@@ -546,7 +546,7 @@ static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf)
        udelay(10);
        lcd_hiu_write(HHI_TCON_PLL_CNTL1, pll_ctrl1);
        udelay(10);
-       lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108);
+       lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x0000110c);
        udelay(10);
        lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10051400);
        udelay(10);
@@ -558,7 +558,7 @@ static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf)
        udelay(10);
        lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 0, LCD_PLL_RST_TL1, 1);
        udelay(10);
-       lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008);
+       lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x0000300c);
 
        ret = lcd_pll_wait_lock(HHI_TCON_PLL_CNTL0, LCD_PLL_LOCK_TL1);
        if (ret) {

diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
index 14f1b69..e9b2777 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
@@ -269,6 +269,8 @@ static char *lcd_ss_level_table_tl1[] = {
        "8, 40000ppm",
        "9, 45000ppm",
        "10, 50000ppm",
+       "11, 55000ppm",
+       "12, 60000ppm",
 };
 
 static char *lcd_ss_freq_table_tl1[] = {
@@ -315,11 +317,13 @@ static unsigned int pll_ss_reg_tl1[][2] = {
        {10,          3}, /* 3: +/-0.75% */
        {10,          4}, /* 4: +/-1.00% */
        {10,          5}, /* 5: +/-1.25% */
-       {10,          6}, /* 1: +/-1.50% */
-       {10,          7}, /* 2: +/-1.75% */
-       {10,          8}, /* 3: +/-2.00% */
-       {10,          9}, /* 4: +/-2.25% */
-       {10,         10}, /* 5: +/-2.50% */
+       {10,          6}, /* 6: +/-1.50% */
+       {10,          7}, /* 7: +/-1.75% */
+       {10,          8}, /* 8: +/-2.00% */
+       {10,          9}, /* 9: +/-2.25% */
+       {10,         10}, /* 10: +/-2.50% */
+       {11,         10}, /* 11: +/-2.75% */
+       {12,         10}, /* 12: +/-3.00% */
 };
 
 /* **********************************