void ve_dnlp_load_reg(void)
{
+ int i;
+
if (dnlp_sel == NEW_DNLP_IN_SHARPNESS) {
if (is_meson_gxlx_cpu() || is_meson_txlx_cpu()) {
- WRITE_VPP_REG(SRSHARP1_DNLP_00, ve_dnlp_reg[0]);
- WRITE_VPP_REG(SRSHARP1_DNLP_01, ve_dnlp_reg[1]);
- WRITE_VPP_REG(SRSHARP1_DNLP_02, ve_dnlp_reg[2]);
- WRITE_VPP_REG(SRSHARP1_DNLP_03, ve_dnlp_reg[3]);
- WRITE_VPP_REG(SRSHARP1_DNLP_04, ve_dnlp_reg[4]);
- WRITE_VPP_REG(SRSHARP1_DNLP_05, ve_dnlp_reg[5]);
- WRITE_VPP_REG(SRSHARP1_DNLP_06, ve_dnlp_reg[6]);
- WRITE_VPP_REG(SRSHARP1_DNLP_07, ve_dnlp_reg[7]);
- WRITE_VPP_REG(SRSHARP1_DNLP_08, ve_dnlp_reg[8]);
- WRITE_VPP_REG(SRSHARP1_DNLP_09, ve_dnlp_reg[9]);
- WRITE_VPP_REG(SRSHARP1_DNLP_10, ve_dnlp_reg[10]);
- WRITE_VPP_REG(SRSHARP1_DNLP_11, ve_dnlp_reg[11]);
- WRITE_VPP_REG(SRSHARP1_DNLP_12, ve_dnlp_reg[12]);
- WRITE_VPP_REG(SRSHARP1_DNLP_13, ve_dnlp_reg[13]);
- WRITE_VPP_REG(SRSHARP1_DNLP_14, ve_dnlp_reg[14]);
- WRITE_VPP_REG(SRSHARP1_DNLP_15, ve_dnlp_reg[15]);
+ for (i = 0; i < 16; i++)
+ WRITE_VPP_REG(SRSHARP1_DNLP_00 + i,
+ ve_dnlp_reg[i]);
+ } else if (is_meson_tl1_cpu()) {
+ for (i = 0; i < 32; i++)
+ WRITE_VPP_REG(SHARP1_DNLP_00 + i,
+ ve_dnlp_reg_v2[i]);
} else {
- WRITE_VPP_REG(SRSHARP0_DNLP_00, ve_dnlp_reg[0]);
- WRITE_VPP_REG(SRSHARP0_DNLP_01, ve_dnlp_reg[1]);
- WRITE_VPP_REG(SRSHARP0_DNLP_02, ve_dnlp_reg[2]);
- WRITE_VPP_REG(SRSHARP0_DNLP_03, ve_dnlp_reg[3]);
- WRITE_VPP_REG(SRSHARP0_DNLP_04, ve_dnlp_reg[4]);
- WRITE_VPP_REG(SRSHARP0_DNLP_05, ve_dnlp_reg[5]);
- WRITE_VPP_REG(SRSHARP0_DNLP_06, ve_dnlp_reg[6]);
- WRITE_VPP_REG(SRSHARP0_DNLP_07, ve_dnlp_reg[7]);
- WRITE_VPP_REG(SRSHARP0_DNLP_08, ve_dnlp_reg[8]);
- WRITE_VPP_REG(SRSHARP0_DNLP_09, ve_dnlp_reg[9]);
- WRITE_VPP_REG(SRSHARP0_DNLP_10, ve_dnlp_reg[10]);
- WRITE_VPP_REG(SRSHARP0_DNLP_11, ve_dnlp_reg[11]);
- WRITE_VPP_REG(SRSHARP0_DNLP_12, ve_dnlp_reg[12]);
- WRITE_VPP_REG(SRSHARP0_DNLP_13, ve_dnlp_reg[13]);
- WRITE_VPP_REG(SRSHARP0_DNLP_14, ve_dnlp_reg[14]);
- WRITE_VPP_REG(SRSHARP0_DNLP_15, ve_dnlp_reg[15]);
+ for (i = 0; i < 16; i++)
+ WRITE_VPP_REG(SRSHARP0_DNLP_00 + i,
+ ve_dnlp_reg[i]);
}
} else {
- /* #endif */
- WRITE_VPP_REG(VPP_DNLP_CTRL_00, ve_dnlp_reg[0]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_01, ve_dnlp_reg[1]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_02, ve_dnlp_reg[2]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_03, ve_dnlp_reg[3]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_04, ve_dnlp_reg[4]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_05, ve_dnlp_reg[5]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_06, ve_dnlp_reg[6]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_07, ve_dnlp_reg[7]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_08, ve_dnlp_reg[8]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_09, ve_dnlp_reg[9]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_10, ve_dnlp_reg[10]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_11, ve_dnlp_reg[11]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_12, ve_dnlp_reg[12]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_13, ve_dnlp_reg[13]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_14, ve_dnlp_reg[14]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_15, ve_dnlp_reg[15]);
+ for (i = 0; i < 16; i++)
+ WRITE_VPP_REG(VPP_DNLP_CTRL_00 + i,
+ ve_dnlp_reg[i]);
}
+
}
static void ve_dnlp_load_def_reg(void)
{
+ int i;
+
if (dnlp_sel == NEW_DNLP_IN_SHARPNESS) {
if (is_meson_gxlx_cpu() || is_meson_txlx_cpu()) {
- WRITE_VPP_REG(SRSHARP1_DNLP_00, ve_dnlp_reg[0]);
- WRITE_VPP_REG(SRSHARP1_DNLP_01, ve_dnlp_reg[1]);
- WRITE_VPP_REG(SRSHARP1_DNLP_02, ve_dnlp_reg[2]);
- WRITE_VPP_REG(SRSHARP1_DNLP_03, ve_dnlp_reg[3]);
- WRITE_VPP_REG(SRSHARP1_DNLP_04, ve_dnlp_reg[4]);
- WRITE_VPP_REG(SRSHARP1_DNLP_05, ve_dnlp_reg[5]);
- WRITE_VPP_REG(SRSHARP1_DNLP_06, ve_dnlp_reg[6]);
- WRITE_VPP_REG(SRSHARP1_DNLP_07, ve_dnlp_reg[7]);
- WRITE_VPP_REG(SRSHARP1_DNLP_08, ve_dnlp_reg[8]);
- WRITE_VPP_REG(SRSHARP1_DNLP_09, ve_dnlp_reg[9]);
- WRITE_VPP_REG(SRSHARP1_DNLP_10, ve_dnlp_reg[10]);
- WRITE_VPP_REG(SRSHARP1_DNLP_11, ve_dnlp_reg[11]);
- WRITE_VPP_REG(SRSHARP1_DNLP_12, ve_dnlp_reg[12]);
- WRITE_VPP_REG(SRSHARP1_DNLP_13, ve_dnlp_reg[13]);
- WRITE_VPP_REG(SRSHARP1_DNLP_14, ve_dnlp_reg[14]);
- WRITE_VPP_REG(SRSHARP1_DNLP_15, ve_dnlp_reg[15]);
+ for (i = 0; i < 16; i++)
+ WRITE_VPP_REG(SRSHARP1_DNLP_00 + i,
+ ve_dnlp_reg[i]);
+ } else if (is_meson_tl1_cpu()) {
+ for (i = 0; i < 32; i++)
+ WRITE_VPP_REG(SHARP1_DNLP_00 + i,
+ ve_dnlp_reg_v2[i]);
} else {
- WRITE_VPP_REG(SRSHARP0_DNLP_00, ve_dnlp_reg[0]);
- WRITE_VPP_REG(SRSHARP0_DNLP_01, ve_dnlp_reg[1]);
- WRITE_VPP_REG(SRSHARP0_DNLP_02, ve_dnlp_reg[2]);
- WRITE_VPP_REG(SRSHARP0_DNLP_03, ve_dnlp_reg[3]);
- WRITE_VPP_REG(SRSHARP0_DNLP_04, ve_dnlp_reg[4]);
- WRITE_VPP_REG(SRSHARP0_DNLP_05, ve_dnlp_reg[5]);
- WRITE_VPP_REG(SRSHARP0_DNLP_06, ve_dnlp_reg[6]);
- WRITE_VPP_REG(SRSHARP0_DNLP_07, ve_dnlp_reg[7]);
- WRITE_VPP_REG(SRSHARP0_DNLP_08, ve_dnlp_reg[8]);
- WRITE_VPP_REG(SRSHARP0_DNLP_09, ve_dnlp_reg[9]);
- WRITE_VPP_REG(SRSHARP0_DNLP_10, ve_dnlp_reg[10]);
- WRITE_VPP_REG(SRSHARP0_DNLP_11, ve_dnlp_reg[11]);
- WRITE_VPP_REG(SRSHARP0_DNLP_12, ve_dnlp_reg[12]);
- WRITE_VPP_REG(SRSHARP0_DNLP_13, ve_dnlp_reg[13]);
- WRITE_VPP_REG(SRSHARP0_DNLP_14, ve_dnlp_reg[14]);
- WRITE_VPP_REG(SRSHARP0_DNLP_15, ve_dnlp_reg[15]);
+ for (i = 0; i < 16; i++)
+ WRITE_VPP_REG(SRSHARP0_DNLP_00 + i,
+ ve_dnlp_reg[i]);
}
} else {
- WRITE_VPP_REG(VPP_DNLP_CTRL_00, ve_dnlp_reg_def[0]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_01, ve_dnlp_reg_def[1]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_02, ve_dnlp_reg_def[2]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_03, ve_dnlp_reg_def[3]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_04, ve_dnlp_reg_def[4]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_05, ve_dnlp_reg_def[5]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_06, ve_dnlp_reg_def[6]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_07, ve_dnlp_reg_def[7]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_08, ve_dnlp_reg_def[8]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_09, ve_dnlp_reg_def[9]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_10, ve_dnlp_reg_def[10]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_11, ve_dnlp_reg_def[11]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_12, ve_dnlp_reg_def[12]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_13, ve_dnlp_reg_def[13]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_14, ve_dnlp_reg_def[14]);
- WRITE_VPP_REG(VPP_DNLP_CTRL_15, ve_dnlp_reg_def[15]);
+ for (i = 0; i < 16; i++)
+ WRITE_VPP_REG(VPP_DNLP_CTRL_00 + i,
+ ve_dnlp_reg_def[i]);
}
}
if (dnlp_sel == NEW_DNLP_IN_SHARPNESS) {
if (is_meson_gxlx_cpu() || is_meson_txlx_cpu())
WRITE_VPP_REG_BITS(SRSHARP1_DNLP_EN, 1, 0, 1);
+ else if (is_meson_tl1_cpu())
+ WRITE_VPP_REG_BITS(SHARP1_DNLP_EN, 1, 0, 1);
else
WRITE_VPP_REG_BITS(SRSHARP0_DNLP_EN, 1, 0, 1);
} else
if (dnlp_sel == NEW_DNLP_IN_SHARPNESS)
if (is_meson_gxlx_cpu() || is_meson_txlx_cpu())
WRITE_VPP_REG_BITS(SRSHARP1_DNLP_EN, 0, 0, 1);
+ else if (is_meson_tl1_cpu())
+ WRITE_VPP_REG_BITS(SHARP1_DNLP_EN, 0, 0, 1);
else
WRITE_VPP_REG_BITS(SRSHARP0_DNLP_EN, 0, 0, 1);
else
WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 0, 1, 1);
}
}
- if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) {
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ vd1_contrast = (READ_VPP_REG(VPP_VADJ1_Y_2) & 0x7ff00) |
+ (cont_val << 0);
+ WRITE_VPP_REG(VPP_VADJ1_Y_2, vd1_contrast);
+ return;
+ } else if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) {
vd1_contrast = (READ_VPP_REG(VPP_VADJ1_Y) & 0x3ff00) |
(cont_val << 0);
} else {
if (bri_val > 1023 || bri_val < -1024)
return;
- if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) {
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ vd1_brightness = (READ_VPP_REG(VPP_VADJ1_Y_2) & 0xff) |
+ (bri_val << 8);
+
+ WRITE_VPP_REG(VPP_VADJ1_Y_2, vd1_brightness);
+ } else if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) {
bri_val = bri_val >> 1;
vd1_brightness = (READ_VPP_REG(VPP_VADJ1_Y) & 0xff) |
(bri_val << 8);
#define AMVECM_MODULE_NAME "amvecm"
#define AMVECM_DEVICE_NAME "amvecm"
#define AMVECM_CLASS_NAME "amvecm"
-#define AMVECM_VER "Ref.2018/09/28"
+#define AMVECM_VER "Ref.2018/11/20"
struct amvecm_dev_s {
unsigned int pq_user_value;
unsigned int hdr_source_type = 0x1;
+#define SR0_OFFSET 0xc00
+#define SR1_OFFSET 0xc80
+unsigned int sr_offset[2] = {0, 0};
+
static int wb_init_bypass_coef[24] = {
0, 0, 0, /* pre offset */
1024, 0, 0,
static int amvecm_set_contrast2(int val)
{
val += 0x80;
- WRITE_VPP_REG_BITS(VPP_VADJ2_Y,
- val, 0, 8);
- WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1);
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ WRITE_VPP_REG_BITS(VPP_VADJ2_Y_2,
+ val, 0, 8);
+ WRITE_VPP_REG_BITS(VPP_VADJ2_MISC, 1, 0, 1);
+
+ } else {
+ WRITE_VPP_REG_BITS(VPP_VADJ2_Y,
+ val, 0, 8);
+ WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1);
+ }
return 0;
}
if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)
WRITE_VPP_REG_BITS(VPP_VADJ2_Y,
vdj_mode_s.brightness2, 8, 9);
+ else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ WRITE_VPP_REG_BITS(VPP_VADJ2_Y_2,
+ vdj_mode_s.brightness2, 8, 11);
else
WRITE_VPP_REG_BITS(VPP_VADJ2_Y,
- vdj_mode_s.brightness2 << 1, 8, 10);
- WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1);
+ vdj_mode_s.brightness2 >> 1, 8, 10);
+
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ WRITE_VPP_REG_BITS(VPP_VADJ2_MISC, 1, 0, 1);
+ else
+ WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1);
return 0;
}
val = (val << 23) >> 23;
return sprintf(buf, "%d\n", val);
+ } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ val = (READ_VPP_REG(VPP_VADJ1_Y_2) >> 8) & 0x7ff;
+ val = (val << 21) >> 21;
+
+ return sprintf(buf, "%d\n", val);
}
val = (READ_VPP_REG(VPP_VADJ1_Y) >> 8) & 0x3ff;
- val = (val << 23) >> 23;
+ val = (val << 22) >> 22;
- return sprintf(buf, "%d\n", val >> 1);
+ return sprintf(buf, "%d\n", val << 1);
}
static ssize_t video_adj1_brightness_store(struct class *cla,
int val;
r = sscanf(buf, "%d\n", &val);
- if ((r != 1) || (val < -255) || (val > 255))
+ if ((r != 1) || (val < -1024) || (val > 1023))
return -EINVAL;
if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)
WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 8, 9);
+ else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ WRITE_VPP_REG_BITS(VPP_VADJ1_Y_2, val, 8, 11);
else
- WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val << 1, 8, 10);
+ WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val >> 1, 8, 10);
- WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1);
+ else
+ WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
return count;
}
static ssize_t video_adj1_contrast_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
- return sprintf(buf, "%d\n",
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ return sprintf(buf, "%d\n",
+ (int)(READ_VPP_REG(VPP_VADJ1_Y_2) & 0xff) - 0x80);
+ else
+ return sprintf(buf, "%d\n",
(int)(READ_VPP_REG(VPP_VADJ1_Y) & 0xff) - 0x80);
}
val += 0x80;
- WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 0, 8);
- WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ WRITE_VPP_REG_BITS(VPP_VADJ1_Y_2, val, 0, 8);
+ WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1);
+ } else {
+ WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 0, 8);
+ WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
+ }
return count;
}
val = (val << 23) >> 23;
return sprintf(buf, "%d\n", val);
+ } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ val = (READ_VPP_REG(VPP_VADJ2_Y_2) >> 8) & 0x7ff;
+ val = (val << 21) >> 21;
+
+ return sprintf(buf, "%d\n", val);
}
val = (READ_VPP_REG(VPP_VADJ2_Y) >> 8) & 0x3ff;
- val = (val << 23) >> 23;
+ val = (val << 22) >> 22;
- return sprintf(buf, "%d\n", val >> 1);
+ return sprintf(buf, "%d\n", val << 1);
}
static ssize_t video_adj2_brightness_store(struct class *cla,
int val;
r = sscanf(buf, "%d\n", &val);
- if ((r != 1) || (val < -255) || (val > 255))
+ if ((r != 1) || (val < -1024) || (val > 1023))
return -EINVAL;
amvecm_set_brightness2(val);
return count;
static ssize_t video_adj2_contrast_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
- return sprintf(buf, "%d\n",
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ return sprintf(buf, "%d\n",
+ (int)(READ_VPP_REG(VPP_VADJ2_Y_2) & 0xff) - 0x80);
+ else
+ return sprintf(buf, "%d\n",
(int)(READ_VPP_REG(VPP_VADJ2_Y) & 0xff) - 0x80);
}
if (mb < -512)
mb = -512;
mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff);
- WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab);
+
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ WRITE_VPP_REG(VPP_VADJ1_MA_MB_2, mab);
+ else
+ WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab);
+
mc = (s16)((mab<<22)>>22); /* mc = -mb */
mc = 0 - mc;
if (mc > 511)
mc = -512;
md = (s16)((mab<<6)>>22); /* md = ma; */
mab = ((mc&0x3ff)<<16)|(md&0x3ff);
- WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab);
- WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
+
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ WRITE_VPP_REG(VPP_VADJ1_MC_MD_2, mab);
+ WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1);
+ } else {
+ WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab);
+ WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
+ }
pr_amvecm_dbg("%s set video_saturation_hue OK!!!\n", __func__);
return 0;
}
mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff);
pr_info("\n[amvideo..] saturation_post:%d hue_post:%d mab:%x\n",
saturation_post, hue_post, mab);
- WRITE_VPP_REG(VPP_VADJ2_MA_MB, mab);
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ WRITE_VPP_REG(VPP_VADJ2_MA_MB_2, mab);
+ else
+ WRITE_VPP_REG(VPP_VADJ2_MA_MB, mab);
mc = (s16)((mab<<22)>>22); /* mc = -mb */
mc = 0 - mc;
if (mc > 511)
mc = -512;
md = (s16)((mab<<6)>>22); /* md = ma; */
mab = ((mc&0x3ff)<<16)|(md&0x3ff);
- WRITE_VPP_REG(VPP_VADJ2_MC_MD, mab);
- WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1);
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ WRITE_VPP_REG(VPP_VADJ2_MC_MD_2, mab);
+ WRITE_VPP_REG_BITS(VPP_VADJ2_MISC, 1, 0, 1);
+ } else {
+ WRITE_VPP_REG(VPP_VADJ2_MC_MD, mab);
+ WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1);
+ }
return 0;
}
static ssize_t amvecm_saturation_hue_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
- return sprintf(buf, "0x%x\n", READ_VPP_REG(VPP_VADJ1_MA_MB));
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ return sprintf(buf, "0x%x\n",
+ READ_VPP_REG(VPP_VADJ1_MA_MB_2));
+ else
+ return sprintf(buf, "0x%x\n",
+ READ_VPP_REG(VPP_VADJ1_MA_MB));
}
static ssize_t amvecm_saturation_hue_store(struct class *cla,
mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff);
pr_info("\n[amvideo..] saturation_pre:%d hue_pre:%d mab:%x\n",
sat_val, hue_val, mab);
- WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab);
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
+ WRITE_VPP_REG(VPP_VADJ1_MA_MB_2, mab);
+ else
+ WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab);
mc = (s16)((mab<<22)>>22); /* mc = -mb */
mc = 0 - mc;
if (mc > 511)
mc = -512;
md = (s16)((mab<<6)>>22); /* md = ma; */
mab = ((mc&0x3ff)<<16)|(md&0x3ff);
- WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab);
- WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
+
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ WRITE_VPP_REG(VPP_VADJ1_MC_MD_2, mab);
+ WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1);
+ } else {
+ WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab);
+ WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1);
+ }
};
static ssize_t amvecm_saturation_hue_pre_show(struct class *cla,
cm_en = 1;
/* sharpness on */
VSYNC_WR_MPEG_REG_BITS(
- SRSHARP0_PK_NR_ENABLE,
+ SRSHARP0_PK_NR_ENABLE + sr_offset[0],
1, 1, 1);
VSYNC_WR_MPEG_REG_BITS(
- SRSHARP1_PK_NR_ENABLE,
+ SRSHARP1_PK_NR_ENABLE + sr_offset[1],
1, 1, 1);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC);
- VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0],
reg_val | 0x10000000);
- VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC,
+ VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1],
reg_val | 0x10000000);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC);
- VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0],
reg_val | 0x10000000);
- VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC,
+ VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1],
reg_val | 0x10000000);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP);
- VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0],
reg_val | 0x4000);
- VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP,
+ VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1],
reg_val | 0x4000);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP);
- VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0],
reg_val | 0x4000);
- VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP,
+ VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1],
reg_val | 0x4000);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL,
- 1, 28, 3);
-
- VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL,
- 1, 28, 3);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 1, 0, 1);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN
+ + sr_offset[0], 7, 0, 3);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL
+ + sr_offset[0], 1, 28, 3);
+
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 1, 0, 1);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN
+ + sr_offset[1], 7, 0, 3);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL
+ + sr_offset[1], 1, 28, 3);
}
VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, 0xd);
pc_mode_last = pc_mode;
cm_en = 0;
VSYNC_WR_MPEG_REG_BITS(
- SRSHARP0_PK_NR_ENABLE,
+ SRSHARP0_PK_NR_ENABLE + sr_offset[0],
0, 1, 1);
VSYNC_WR_MPEG_REG_BITS(
- SRSHARP1_PK_NR_ENABLE,
+ SRSHARP1_PK_NR_ENABLE + sr_offset[1],
0, 1, 1);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC);
- VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0],
reg_val & 0xefffffff);
- VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC,
+ VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1],
reg_val & 0xefffffff);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC);
- VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0],
reg_val & 0xefffffff);
- VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC,
+ VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1],
reg_val & 0xefffffff);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP);
- VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0],
reg_val & 0xffffbfff);
- VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP,
+ VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1],
reg_val & 0xffffbfff);
- reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP);
- VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP,
+ reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP
+ + sr_offset[0]);
+ VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0],
reg_val & 0xffffbfff);
- VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP,
+ VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1],
reg_val & 0xffffbfff);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL,
- 0, 28, 3);
-
- VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3);
- VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL,
- 0, 28, 3);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 0, 0, 1);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN
+ + sr_offset[0], 0, 0, 3);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL
+ + sr_offset[0], 0, 28, 3);
+
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 0, 0, 1);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN
+ + sr_offset[1], 0, 0, 3);
+ VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL
+ + sr_offset[1], 0, 28, 3);
}
VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, 0x0);
pc_mode_last = pc_mode;
void amvecm_sr0_pk_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
+ 1, 1, 1);
else
- WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
+ 0, 1, 1);
}
void amvecm_sr1_pk_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1],
+ 1, 1, 1);
else
- WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1],
+ 0, 1, 1);
}
void amvecm_sr0_dering_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0],
+ 1, 28, 3);
else
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0],
+ 0, 28, 3);
}
void amvecm_sr1_dering_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1],
+ 1, 28, 3);
else
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1],
+ 0, 28, 3);
}
void amvecm_sr0_dejaggy_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 1, 0, 1);
else
- WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 0, 0, 1);
}
void amvecm_sr1_dejaggy_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 1, 0, 1);
else
- WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 0, 0, 1);
}
void amvecm_sr0_derection_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0],
+ 7, 0, 3);
else
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0],
+ 0, 0, 3);
}
void amvecm_sr1_derection_enable(unsigned int enable)
{
if (enable)
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1],
+ 7, 0, 3);
else
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1],
+ 0, 0, 3);
}
void pq_user_latch_process(void)
/*2:lti/cti enable 3:lti/cti disable*/
switch (sel) {
case 0:
- WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
+ 1, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1],
+ 1, 1, 1);
break;
case 1:
- WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
+ 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1],
+ 0, 1, 1);
break;
case 2:
- WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 1, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 1, 14, 1);
-
- WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 1, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 1, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0],
+ 1, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0],
+ 1, 14, 1);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1],
+ 1, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1],
+ 1, 14, 1);
break;
case 3:
- WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 0, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 0, 14, 1);
-
- WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0],
+ 0, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0],
+ 0, 14, 1);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1],
+ 0, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1],
+ 0, 14, 1);
break;
/*sr4 drtlpf theta en*/
case 4:
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 4, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 3, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0],
+ 7, 4, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1],
+ 7, 3, 3);
break;
case 5:
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 4, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 3, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0],
+ 0, 4, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1],
+ 0, 3, 3);
break;
/*sr4 debanding en*/
case 6:
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 23, 1);
-
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 23, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 23, 1);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 23, 1);
break;
case 7:
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 23, 1);
-
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 23, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 23, 1);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 23, 1);
break;
/*sr3 dejaggy en*/
case 8:
- WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 1, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 1, 0, 1);
break;
case 9:
- WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 0, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 0, 0, 1);
break;
/*sr3 dering en*/
case 10:
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0],
+ 1, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1],
+ 1, 28, 3);
break;
case 11:
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0],
+ 0, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1],
+ 0, 28, 3);
break;
/*sr3 derection lpf en*/
case 12:
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0],
+ 7, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1],
+ 7, 0, 3);
break;
case 13:
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0],
+ 0, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1],
+ 0, 0, 3);
break;
default:
if (!is_dolby_vision_enable())
#endif
amcm_enable();
- WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1);
-
- WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 1, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 1, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 1, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 1, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 1, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
+ 1, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1],
+ 1, 1, 1);
- if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3);
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0],
+ 1, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0],
+ 1, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1],
+ 1, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1],
+ 1, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1],
+ 1, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3);
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
+ WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 1, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN
+ + sr_offset[0], 7, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL
+ + sr_offset[0], 1, 28, 3);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 1, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN
+ + sr_offset[1], 7, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL
+ + sr_offset[1], 1, 28, 3);
}
/*sr4 drtlpf theta/ debanding en*/
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) {
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 4, 3);
-
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 23, 1);
-
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 23, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN
+ + sr_offset[0], 7, 4, 3);
+
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 1, 23, 1);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 1, 23, 1);
}
amvecm_wb_enable(true);
amcm_disable();
- WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
+ 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1],
+ 0, 1, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 0, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 0, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 0, 28, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0],
+ 0, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0],
+ 0, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1],
+ 0, 28, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1],
+ 0, 14, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1],
+ 0, 14, 1);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3);
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3);
-
- WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3);
- WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0],
+ 0, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN
+ + sr_offset[0], 0, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL
+ + sr_offset[0], 0, 28, 3);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1],
+ 0, 0, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN
+ + sr_offset[1], 0, 0, 3);
+ WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL
+ + sr_offset[1], 0, 28, 3);
}
/*sr4 drtlpf theta/ debanding en*/
if (is_meson_txlx_cpu()) {
- WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 4, 3);
-
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 23, 1);
-
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 4, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 5, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 22, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 23, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN
+ + sr_offset[0], 0, 4, 3);
+
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0],
+ 0, 23, 1);
+
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 4, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 5, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 22, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1],
+ 0, 23, 1);
}
amvecm_wb_enable(false);
kfree(hist);
}
+static void cm_init_config(void)
+{
+ WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, XVYCC_YSCP_REG);
+ WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x3ff0000);
+ WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, XVYCC_USCP_REG);
+ WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x3ff0000);
+ WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, XVYCC_VSCP_REG);
+ WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x3ff0000);
+ WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ0_REG);
+ WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x40400);
+}
+
static const char *amvecm_debug_usage_str = {
"Usage:\n"
"echo vpp_size > /sys/class/amvecm/debug; get vpp size config\n"
/* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */
void init_pq_setting(void)
{
+ if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
+ /*sr0 & sr1 register shfit*/
+ sr_offset[0] = SR0_OFFSET;
+ sr_offset[1] = SR1_OFFSET;
+ /*cm register init*/
+ cm_init_config();
+ /*lc init*/
+ lc_init();
+ }
/*probe close sr0 peaking for switch on video*/
WRITE_VPP_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1);
- WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 1, 0, 1);
+ WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 0, 0, 1);
/*default dnlp off*/
- WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1);
- WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
+ 0, 1, 1);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1],
+ 0, 1, 1);
WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 0, DNLP_EN_BIT, DNLP_EN_WID);
/*end*/
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) {
- WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP, 2, 16, 2);
+ WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP + sr_offset[1],
+ 2, 16, 2);
/*sr0 sr1 chroma filter bypass*/
- WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_HCOEF0, 0x4000);
- WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_VCOEF0, 0x4000);
- WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_HCOEF0, 0x4000);
- WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_VCOEF0, 0x4000);
+ WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_HCOEF0 + sr_offset[0],
+ 0x4000);
+ WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_VCOEF0 + sr_offset[0],
+ 0x4000);
+ WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_HCOEF0 + sr_offset[1],
+ 0x4000);
+ WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_VCOEF0 + sr_offset[1],
+ 0x4000);
}
if (is_meson_gxlx_cpu())
amve_sharpness_init();
/*dnlp alg parameters init*/
dnlp_alg_param_init();
-
- if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
- lc_init();
}
/* #endif*/
#define ENCL_VIDEO_EN 0x1ca0
+/*TL1 VADJ1&VADJ2*/
+#define VPP_VADJ1_MISC 0x3280
+#define VPP_VADJ1_BLACK_VAL 0x3281
+#define VPP_VADJ1_Y_2 0x3282
+#define VPP_VADJ1_MA_MB_2 0x3283
+#define VPP_VADJ1_MC_MD_2 0x3284
+
+#define VPP_VADJ2_MISC 0x32a0
+#define VPP_VADJ2_BLACK_VAL 0x32a1
+#define VPP_VADJ2_Y_2 0x32a2
+#define VPP_VADJ2_MA_MB_2 0x32a3
+#define VPP_VADJ2_MC_MD_2 0x32a4
+
/*TL1 add cm hist reg*/
+#define XVYCC_YSCP_REG 0x21c
+#define XVYCC_USCP_REG 0x21d
+#define XVYCC_VSCP_REG 0x21e
#define LUMA_ADJ0_REG 0x21f
#define LUMA_ADJ1_REG 0x220
#define STA_WIN_XYXY0_REG 0x221
#define RO_CM_BRT_BIN 0x267
/*TL1 cm HIST reg end*/
+/*TL1 SHARPNESS REG*/
+#define SHARP0_SHARP_HVSIZE 0x3e00
+#define SHARP0_SHARP_HVBLANK_NUM 0x3e01
+#define SHARP0_NR_GAUSSIAN_MODE 0x3e02
+#define SHARP0_PK_CON_2CIRHPGAIN_TH_RATE 0x3e05
+#define SHARP0_PK_CON_2CIRHPGAIN_LIMIT 0x3e06
+#define SHARP0_PK_CON_2CIRBPGAIN_TH_RATE 0x3e07
+#define SHARP0_PK_CON_2CIRBPGAIN_LIMIT 0x3e08
+#define SHARP0_PK_CON_2DRTHPGAIN_TH_RATE 0x3e09
+#define SHARP0_PK_CON_2DRTHPGAIN_LIMIT 0x3e0a
+#define SHARP0_PK_CON_2DRTBPGAIN_TH_RATE 0x3e0b
+#define SHARP0_PK_CON_2DRTBPGAIN_LIMIT 0x3e0c
+#define SHARP0_PK_CIRFB_LPF_MODE 0x3e0d
+#define SHARP0_PK_DRTFB_LPF_MODE 0x3e0e
+#define SHARP0_PK_CIRFB_HP_CORING 0x3e0f
+#define SHARP0_PK_CIRFB_BP_CORING 0x3e10
+#define SHARP0_PK_DRTFB_HP_CORING 0x3e11
+#define SHARP0_PK_DRTFB_BP_CORING 0x3e12
+#define SHARP0_PK_CIRFB_BLEND_GAIN 0x3e13
+#define SHARP0_NR_ALPY_SSD_GAIN_OFST 0x3e14
+#define SHARP0_NR_ALP0Y_ERR2CURV_TH_RATE 0x3e15
+#define SHARP0_NR_ALP0Y_ERR2CURV_LIMIT 0x3e16
+#define SHARP0_NR_ALP0C_ERR2CURV_TH_RATE 0x3e17
+#define SHARP0_NR_ALP0C_ERR2CURV_LIMIT 0x3e18
+#define SHARP0_NR_ALP0_MIN_MAX 0x3e19
+#define SHARP0_NR_ALP1_MIERR_CORING 0x3e1a
+#define SHARP0_NR_ALP1_ERR2CURV_TH_RATE 0x3e1b
+#define SHARP0_NR_ALP1_ERR2CURV_LIMIT 0x3e1c
+#define SHARP0_NR_ALP1_MIN_MAX 0x3e1d
+#define SHARP0_PK_ALP2_MIERR_CORING 0x3e1e
+#define SHARP0_PK_ALP2_ERR2CURV_TH_RATE 0x3e1f
+#define SHARP0_PK_ALP2_ERR2CURV_LIMIT 0x3e20
+#define SHARP0_PK_ALP2_MIN_MAX 0x3e21
+#define SHARP0_PK_FINALGAIN_HP_BP 0x3e22
+#define SHARP0_PK_OS_HORZ_CORE_GAIN 0x3e23
+#define SHARP0_PK_OS_VERT_CORE_GAIN 0x3e24
+#define SHARP0_PK_OS_ADPT_MISC 0x3e25
+#define SHARP0_PK_OS_STATIC 0x3e26
+#define SHARP0_PK_NR_ENABLE 0x3e27
+#define SHARP0_PK_DRT_SAD_MISC 0x3e28
+#define SHARP0_NR_TI_DNLP_BLEND 0x3e29
+#define SHARP0_TI_DIR_CORE_ALPHA 0x3e2a
+#define SHARP0_CTI_DIR_ALPHA 0x3e2b
+#define SHARP0_LTI_CTI_DF_GAIN 0x3e2c
+#define SHARP0_LTI_CTI_DIR_AC_DBG 0x3e2d
+#define SHARP0_HCTI_FLT_CLP_DC 0x3e2e
+#define SHARP0_HCTI_BST_GAIN 0x3e2f
+#define SHARP0_HCTI_BST_CORE 0x3e30
+#define SHARP0_HCTI_CON_2_GAIN_0 0x3e31
+#define SHARP0_HCTI_CON_2_GAIN_1 0x3e32
+#define SHARP0_HCTI_OS_MARGIN 0x3e33
+#define SHARP0_HLTI_FLT_CLP_DC 0x3e34
+#define SHARP0_HLTI_BST_GAIN 0x3e35
+#define SHARP0_HLTI_BST_CORE 0x3e36
+#define SHARP0_HLTI_CON_2_GAIN_0 0x3e37
+#define SHARP0_HLTI_CON_2_GAIN_1 0x3e38
+#define SHARP0_HLTI_OS_MARGIN 0x3e39
+#define SHARP0_VLTI_FLT_CON_CLP 0x3e3a
+#define SHARP0_VLTI_BST_GAIN 0x3e3b
+#define SHARP0_VLTI_BST_CORE 0x3e3c
+#define SHARP0_VLTI_CON_2_GAIN_0 0x3e3d
+#define SHARP0_VLTI_CON_2_GAIN_1 0x3e3e
+#define SHARP0_VCTI_FLT_CON_CLP 0x3e3f
+#define SHARP0_VCTI_BST_GAIN 0x3e40
+#define SHARP0_VCTI_BST_CORE 0x3e41
+#define SHARP0_VCTI_CON_2_GAIN_0 0x3e42
+#define SHARP0_VCTI_CON_2_GAIN_1 0x3e43
+#define SHARP0_SHARP_3DLIMIT 0x3e44
+#define SHARP0_DNLP_EN 0x3e45
+#define SHARP0_DEMO_CRTL 0x3e56
+#define SHARP0_SHARP_SR2_CTRL 0x3e57
+#define SHARP0_SHARP_SR2_YBIC_HCOEF0 0x3e58
+#define SHARP0_SHARP_SR2_YBIC_HCOEF1 0x3e59
+#define SHARP0_SHARP_SR2_CBIC_HCOEF0 0x3e5a
+#define SHARP0_SHARP_SR2_CBIC_HCOEF1 0x3e5b
+#define SHARP0_SHARP_SR2_YBIC_VCOEF0 0x3e5c
+#define SHARP0_SHARP_SR2_YBIC_VCOEF1 0x3e5d
+#define SHARP0_SHARP_SR2_CBIC_VCOEF0 0x3e5e
+#define SHARP0_SHARP_SR2_CBIC_VCOEF1 0x3e5f
+#define SHARP0_SHARP_SR2_MISC 0x3e60
+#define SHARP0_SR3_SAD_CTRL 0x3e61
+#define SHARP0_SR3_PK_CTRL0 0x3e62
+#define SHARP0_SR3_PK_CTRL1 0x3e63
+#define SHARP0_DEJ_CTRL 0x3e64
+#define SHARP0_DEJ_ALPHA 0x3e65
+#define SHARP0_SR3_DRTLPF_EN 0x3e66
+#define SHARP0_SR3_DRTLPF_ALPHA_0 0x3e67
+#define SHARP0_SR3_DRTLPF_ALPHA_1 0x3e68
+#define SHARP0_SR3_DRTLPF_ALPHA_2 0x3e69
+#define SHARP0_SR3_DRTLPF_ALPHA_OFST 0x3e6a
+#define SHARP0_SR3_DERING_CTRL 0x3e6b
+#define SHARP0_SR3_DERING_LUMA2PKGAIN_0TO3 0x3e6c
+#define SHARP0_SR3_DERING_LUMA2PKGAIN_4TO6 0x3e6d
+#define SHARP0_SR3_DERING_LUMA2PKOS_0TO3 0x3e6e
+#define SHARP0_SR3_DERING_LUMA2PKOS_4TO6 0x3e6f
+#define SHARP0_SR3_DERING_GAINVS_MADSAD 0x3e70
+#define SHARP0_SR3_DERING_GAINVS_VR2MAX 0x3e71
+#define SHARP0_SR3_DERING_PARAM0 0x3e72
+#define SHARP0_SR3_DRTLPF_THETA 0x3e73
+#define SHARP0_SATPRT_CTRL 0x3e74
+#define SHARP0_SATPRT_DIVM 0x3e75
+#define SHARP0_DB_FLT_CTRL 0x3e77
+#define SHARP0_DB_FLT_YC_THRD 0x3e78
+#define SHARP0_DB_FLT_RANDLUT 0x3e79
+#define SHARP0_DB_FLT_PXI_THRD 0x3e7a
+#define SHARP0_DB_FLT_SEED_Y 0x3e7b
+#define SHARP0_DB_FLT_SEED_U 0x3e7c
+#define SHARP0_DB_FLT_SEED_V 0x3e7d
+#define SHARP0_PKGAIN_VSLUMA_LUT_L 0x3e7e
+#define SHARP0_PKGAIN_VSLUMA_LUT_H 0x3e7f
+#define SHARP0_PKOSHT_VSLUMA_LUT_L 0x3e80
+#define SHARP0_PKOSHT_VSLUMA_LUT_H 0x3e81
+#define SHARP0_SATPRT_LMT_RGB1 0x3e82
+#define SHARP0_SATPRT_LMT_RGB2 0x3e83
+#define SHARP0_SHARP_GATE_CLK_CTRL_0 0x3e84
+#define SHARP0_SHARP_GATE_CLK_CTRL_1 0x3e85
+#define SHARP0_SHARP_GATE_CLK_CTRL_2 0x3e86
+#define SHARP0_SHARP_GATE_CLK_CTRL_3 0x3e87
+#define SHARP0_SHARP_DPS_CTRL 0x3e88
+#define SHARP0_DNLP_00 0x3e90
+#define SHARP0_DNLP_01 0x3e91
+#define SHARP0_DNLP_02 0x3e92
+#define SHARP0_DNLP_03 0x3e93
+#define SHARP0_DNLP_04 0x3e94
+#define SHARP0_DNLP_05 0x3e95
+#define SHARP0_DNLP_06 0x3e96
+#define SHARP0_DNLP_07 0x3e97
+#define SHARP0_DNLP_08 0x3e98
+#define SHARP0_DNLP_09 0x3e99
+#define SHARP0_DNLP_10 0x3e9a
+#define SHARP0_DNLP_11 0x3e9b
+#define SHARP0_DNLP_12 0x3e9c
+#define SHARP0_DNLP_13 0x3e9d
+#define SHARP0_DNLP_14 0x3e9e
+#define SHARP0_DNLP_15 0x3e9f
+#define SHARP0_DNLP_16 0x3ea0
+#define SHARP0_DNLP_17 0x3ea1
+#define SHARP0_DNLP_18 0x3ea2
+#define SHARP0_DNLP_19 0x3ea3
+#define SHARP0_DNLP_20 0x3ea4
+#define SHARP0_DNLP_21 0x3ea5
+#define SHARP0_DNLP_22 0x3ea6
+#define SHARP0_DNLP_23 0x3ea7
+#define SHARP0_DNLP_24 0x3ea8
+#define SHARP0_DNLP_25 0x3ea9
+#define SHARP0_DNLP_26 0x3eaa
+#define SHARP0_DNLP_27 0x3eab
+#define SHARP0_DNLP_28 0x3eac
+#define SHARP0_DNLP_29 0x3ead
+#define SHARP0_DNLP_30 0x3eae
+#define SHARP0_DNLP_31 0x3eaf
+#define SHARP0_SHARP_SYNC_CTRL 0x3eb0
+#define SHARP1_SHARP_HVSIZE 0x3f00
+#define SHARP1_SHARP_HVBLANK_NUM 0x3f01
+#define SHARP1_NR_GAUSSIAN_MODE 0x3f02
+#define SHARP1_PK_CON_2CIRHPGAIN_TH_RATE 0x3f05
+#define SHARP1_PK_CON_2CIRHPGAIN_LIMIT 0x3f06
+#define SHARP1_PK_CON_2CIRBPGAIN_TH_RATE 0x3f07
+#define SHARP1_PK_CON_2CIRBPGAIN_LIMIT 0x3f08
+#define SHARP1_PK_CON_2DRTHPGAIN_TH_RATE 0x3f09
+#define SHARP1_PK_CON_2DRTHPGAIN_LIMIT 0x3f0a
+#define SHARP1_PK_CON_2DRTBPGAIN_TH_RATE 0x3f0b
+#define SHARP1_PK_CON_2DRTBPGAIN_LIMIT 0x3f0c
+#define SHARP1_PK_CIRFB_LPF_MODE 0x3f0d
+#define SHARP1_PK_DRTFB_LPF_MODE 0x3f0e
+#define SHARP1_PK_CIRFB_HP_CORING 0x3f0f
+#define SHARP1_PK_CIRFB_BP_CORING 0x3f10
+#define SHARP1_PK_DRTFB_HP_CORING 0x3f11
+#define SHARP1_PK_DRTFB_BP_CORING 0x3f12
+#define SHARP1_PK_CIRFB_BLEND_GAIN 0x3f13
+#define SHARP1_NR_ALPY_SSD_GAIN_OFST 0x3f14
+#define SHARP1_NR_ALP0Y_ERR2CURV_TH_RATE 0x3f15
+#define SHARP1_NR_ALP0Y_ERR2CURV_LIMIT 0x3f16
+#define SHARP1_NR_ALP0C_ERR2CURV_TH_RATE 0x3f17
+#define SHARP1_NR_ALP0C_ERR2CURV_LIMIT 0x3f18
+#define SHARP1_NR_ALP0_MIN_MAX 0x3f19
+#define SHARP1_NR_ALP1_MIERR_CORING 0x3f1a
+#define SHARP1_NR_ALP1_ERR2CURV_TH_RATE 0x3f1b
+#define SHARP1_NR_ALP1_ERR2CURV_LIMIT 0x3f1c
+#define SHARP1_NR_ALP1_MIN_MAX 0x3f1d
+#define SHARP1_PK_ALP2_MIERR_CORING 0x3f1e
+#define SHARP1_PK_ALP2_ERR2CURV_TH_RATE 0x3f1f
+#define SHARP1_PK_ALP2_ERR2CURV_LIMIT 0x3f20
+#define SHARP1_PK_ALP2_MIN_MAX 0x3f21
+#define SHARP1_PK_FINALGAIN_HP_BP 0x3f22
+#define SHARP1_PK_OS_HORZ_CORE_GAIN 0x3f23
+#define SHARP1_PK_OS_VERT_CORE_GAIN 0x3f24
+#define SHARP1_PK_OS_ADPT_MISC 0x3f25
+#define SHARP1_PK_OS_STATIC 0x3f26
+#define SHARP1_PK_NR_ENABLE 0x3f27
+#define SHARP1_PK_DRT_SAD_MISC 0x3f28
+#define SHARP1_NR_TI_DNLP_BLEND 0x3f29
+#define SHARP1_TI_DIR_CORE_ALPHA 0x3f2a
+#define SHARP1_CTI_DIR_ALPHA 0x3f2b
+#define SHARP1_LTI_CTI_DF_GAIN 0x3f2c
+#define SHARP1_LTI_CTI_DIR_AC_DBG 0x3f2d
+#define SHARP1_HCTI_FLT_CLP_DC 0x3f2e
+#define SHARP1_HCTI_BST_GAIN 0x3f2f
+#define SHARP1_HCTI_BST_CORE 0x3f30
+#define SHARP1_HCTI_CON_2_GAIN_0 0x3f31
+#define SHARP1_HCTI_CON_2_GAIN_1 0x3f32
+#define SHARP1_HCTI_OS_MARGIN 0x3f33
+#define SHARP1_HLTI_FLT_CLP_DC 0x3f34
+#define SHARP1_HLTI_BST_GAIN 0x3f35
+#define SHARP1_HLTI_BST_CORE 0x3f36
+#define SHARP1_HLTI_CON_2_GAIN_0 0x3f37
+#define SHARP1_HLTI_CON_2_GAIN_1 0x3f38
+#define SHARP1_HLTI_OS_MARGIN 0x3f39
+#define SHARP1_VLTI_FLT_CON_CLP 0x3f3a
+#define SHARP1_VLTI_BST_GAIN 0x3f3b
+#define SHARP1_VLTI_BST_CORE 0x3f3c
+#define SHARP1_VLTI_CON_2_GAIN_0 0x3f3d
+#define SHARP1_VLTI_CON_2_GAIN_1 0x3f3e
+#define SHARP1_VCTI_FLT_CON_CLP 0x3f3f
+#define SHARP1_VCTI_BST_GAIN 0x3f40
+#define SHARP1_VCTI_BST_CORE 0x3f41
+#define SHARP1_VCTI_CON_2_GAIN_0 0x3f42
+#define SHARP1_VCTI_CON_2_GAIN_1 0x3f43
+#define SHARP1_SHARP_3DLIMIT 0x3f44
+#define SHARP1_DNLP_EN 0x3f45
+#define SHARP1_DEMO_CRTL 0x3f56
+#define SHARP1_SHARP_SR2_CTRL 0x3f57
+#define SHARP1_SHARP_SR2_YBIC_HCOEF0 0x3f58
+#define SHARP1_SHARP_SR2_YBIC_HCOEF1 0x3f59
+#define SHARP1_SHARP_SR2_CBIC_HCOEF0 0x3f5a
+#define SHARP1_SHARP_SR2_CBIC_HCOEF1 0x3f5b
+#define SHARP1_SHARP_SR2_YBIC_VCOEF0 0x3f5c
+#define SHARP1_SHARP_SR2_YBIC_VCOEF1 0x3f5d
+#define SHARP1_SHARP_SR2_CBIC_VCOEF0 0x3f5e
+#define SHARP1_SHARP_SR2_CBIC_VCOEF1 0x3f5f
+#define SHARP1_SHARP_SR2_MISC 0x3f60
+#define SHARP1_SR3_SAD_CTRL 0x3f61
+#define SHARP1_SR3_PK_CTRL0 0x3f62
+#define SHARP1_SR3_PK_CTRL1 0x3f63
+#define SHARP1_DEJ_CTRL 0x3f64
+#define SHARP1_DEJ_ALPHA 0x3f65
+#define SHARP1_SR3_DRTLPF_EN 0x3f66
+#define SHARP1_SR3_DRTLPF_ALPHA_0 0x3f67
+#define SHARP1_SR3_DRTLPF_ALPHA_1 0x3f68
+#define SHARP1_SR3_DRTLPF_ALPHA_2 0x3f69
+#define SHARP1_SR3_DRTLPF_ALPHA_OFST 0x3f6a
+#define SHARP1_SR3_DERING_CTRL 0x3f6b
+#define SHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 0x3f6c
+#define SHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 0x3f6d
+#define SHARP1_SR3_DERING_LUMA2PKOS_0TO3 0x3f6e
+#define SHARP1_SR3_DERING_LUMA2PKOS_4TO6 0x3f6f
+#define SHARP1_SR3_DERING_GAINVS_MADSAD 0x3f70
+#define SHARP1_SR3_DERING_GAINVS_VR2MAX 0x3f71
+#define SHARP1_SR3_DERING_PARAM0 0x3f72
+#define SHARP1_SR3_DRTLPF_THETA 0x3f73
+#define SHARP1_SATPRT_CTRL 0x3f74
+#define SHARP1_SATPRT_DIVM 0x3f75
+#define SHARP1_DB_FLT_CTRL 0x3f77
+#define SHARP1_DB_FLT_YC_THRD 0x3f78
+#define SHARP1_DB_FLT_RANDLUT 0x3f79
+#define SHARP1_DB_FLT_PXI_THRD 0x3f7a
+#define SHARP1_DB_FLT_SEED_Y 0x3f7b
+#define SHARP1_DB_FLT_SEED_U 0x3f7c
+#define SHARP1_DB_FLT_SEED_V 0x3f7d
+#define SHARP1_PKGAIN_VSLUMA_LUT_L 0x3f7e
+#define SHARP1_PKGAIN_VSLUMA_LUT_H 0x3f7f
+#define SHARP1_PKOSHT_VSLUMA_LUT_L 0x3f80
+#define SHARP1_PKOSHT_VSLUMA_LUT_H 0x3f81
+#define SHARP1_SATPRT_LMT_RGB1 0x3f82
+#define SHARP1_SATPRT_LMT_RGB2 0x3f83
+#define SHARP1_SHARP_GATE_CLK_CTRL_0 0x3f84
+#define SHARP1_SHARP_GATE_CLK_CTRL_1 0x3f85
+#define SHARP1_SHARP_GATE_CLK_CTRL_2 0x3f86
+#define SHARP1_SHARP_GATE_CLK_CTRL_3 0x3f87
+#define SHARP1_SHARP_DPS_CTRL 0x3f88
+#define SHARP1_DNLP_00 0x3f90
+#define SHARP1_DNLP_01 0x3f91
+#define SHARP1_DNLP_02 0x3f92
+#define SHARP1_DNLP_03 0x3f93
+#define SHARP1_DNLP_04 0x3f94
+#define SHARP1_DNLP_05 0x3f95
+#define SHARP1_DNLP_06 0x3f96
+#define SHARP1_DNLP_07 0x3f97
+#define SHARP1_DNLP_08 0x3f98
+#define SHARP1_DNLP_09 0x3f99
+#define SHARP1_DNLP_10 0x3f9a
+#define SHARP1_DNLP_11 0x3f9b
+#define SHARP1_DNLP_12 0x3f9c
+#define SHARP1_DNLP_13 0x3f9d
+#define SHARP1_DNLP_14 0x3f9e
+#define SHARP1_DNLP_15 0x3f9f
+#define SHARP1_DNLP_16 0x3fa0
+#define SHARP1_DNLP_17 0x3fa1
+#define SHARP1_DNLP_18 0x3fa2
+#define SHARP1_DNLP_19 0x3fa3
+#define SHARP1_DNLP_20 0x3fa4
+#define SHARP1_DNLP_21 0x3fa5
+#define SHARP1_DNLP_22 0x3fa6
+#define SHARP1_DNLP_23 0x3fa7
+#define SHARP1_DNLP_24 0x3fa8
+#define SHARP1_DNLP_25 0x3fa9
+#define SHARP1_DNLP_26 0x3faa
+#define SHARP1_DNLP_27 0x3fab
+#define SHARP1_DNLP_28 0x3fac
+#define SHARP1_DNLP_29 0x3fad
+#define SHARP1_DNLP_30 0x3fae
+#define SHARP1_DNLP_31 0x3faf
+#define SHARP1_SHARP_SYNC_CTRL 0x3fb0
+/*TL1 SHARPNESS REG END*/
+
/*LC register begin*/
#define SRSHARP1_LC_INPUT_MUX 0x3fb1
#define SRSHARP1_LC_TOP_CTRL 0x3fc0