ARM: OMAP5: set mmc clock frequency to 192MHz

Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index ee2e78b..3d718c0 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -135,7 +135,7 @@
 
 /* CM_L3INIT_HSMMCn_CLKCTRL */
 #define HSMMC_CLKCTRL_CLKSEL_MASK              (1 << 24)
-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK          (1 << 25)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK          (3 << 25)
 
 /* CM_L3INIT_SATA_CLKCTRL */
 #define SATA_CLKCTRL_OPTFCLKEN_MASK            (1 << 8)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index c6129c5..3d70148 100644 (file)
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -199,7 +199,11 @@ struct omap_hsmmc_plat {
 #define MMC_CMD0       (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
 /* Clock Configurations and Macros */
+#ifdef CONFIG_OMAP54XX
+#define MMC_CLOCK_REFERENCE    192 /* MHz */
+#else
 #define MMC_CLOCK_REFERENCE    96 /* MHz */
+#endif
 
 /* DLL */
 #define DLL_SWT                        BIT(20)

diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index bb05e19..7fc3836 100644 (file)
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -438,17 +438,17 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
                        GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 
-       /* Enable 96 MHz clock for MMC1 & MMC2 */
+       /* Enable 192 MHz clock for MMC1 & MMC2 */
        setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
        setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
 
        /* Set the correct clock dividers for mmc */
-       setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
-                       HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-       setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
-                       HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+       clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+                    HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+       clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+                    HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 
        /* Select 32KHz clock as the source of GPTIMER1 */
        setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,