mpc83xx: Fix the SATA clock setting of 837x targets

Currently the SATA controller clock is configured as CSB clock,
usually the CSB clock is 400/333/266MHz.

However, The SATA IP block is only guaranteed to operate up to
200 MHz as stated in the HW spec.

The bug is reported by Joe D'Abbraccio <ljd015@freescale.com>

This patch makes the SATA clock as half of CSB clock.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 7c4e76e..7fc0f7e 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -96,7 +96,7 @@
  */
 #define CFG_SCCR_TSEC1CM       1       /* CSB:eTSEC1 = 1:1 */
 #define CFG_SCCR_TSEC2CM       1       /* CSB:eTSEC2 = 1:1 */
-#define CFG_SCCR_SATACM                SCCR_SATACM_1   /* CSB:SATA[0:3] = 1:1 */
+#define CFG_SCCR_SATACM                SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
 
 /*
  * System IO Config

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index eaac525..c698ff8 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -108,7 +108,7 @@
 /* System Clock Configuration Register */
 #define CFG_SCCR_TSEC1CM       1               /* eTSEC1 clock mode (0-3) */
 #define CFG_SCCR_TSEC2CM       1               /* eTSEC2 clock mode (0-3) */
-#define CFG_SCCR_SATACM                SCCR_SATACM_1   /* SATA1-4 clock mode (0-3) */
+#define CFG_SCCR_SATACM                SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
 
 /*
  * System IO Config