{
struct dw_mci *host = dev_id;
u32 pending;
- unsigned int pass_count = 0;
int i;
- do {
- pending = mci_readl(host, MINTSTS); /* read-only mask reg */
+ pending = mci_readl(host, MINTSTS); /* read-only mask reg */
+
+ if (pending) {
/*
* DTO fix - version 2.10a and below, and only if internal DMA
pending |= SDMMC_INT_DATA_OVER;
}
- if (!pending)
- break;
-
if (pending & DW_MCI_CMD_ERROR_FLAGS) {
mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
host->cmd_status = pending;
}
}
- } while (pass_count++ < 5);
+ }
#ifdef CONFIG_MMC_DW_IDMAC
/* Handle DMA interrupts */