rockchip: gpio: Add rockchip GPIO driver

This supports RK3288 at present. It does not implement functions or support
for pull up/down.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
new file mode 100644 (file)
index 0000000..e39218d
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+struct rockchip_gpio_regs {
+       u32 swport_dr;
+       u32 swport_ddr;
+       u32 reserved0[(0x30 - 0x08) / 4];
+       u32 inten;
+       u32 intmask;
+       u32 inttype_level;
+       u32 int_polarity;
+       u32 int_status;
+       u32 int_rawstatus;
+       u32 debounce;
+       u32 porta_eoi;
+       u32 ext_port;
+       u32 reserved1[(0x60 - 0x54) / 4];
+       u32 ls_sync;
+};
+check_member(rockchip_gpio_regs, ls_sync, 0x60);
+
+#endif

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 9a5d29d..ef57a89 100644 (file)
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -28,6 +28,15 @@ config LPC32XX_GPIO
        help
          Support for the LPC32XX GPIO driver.
 
+config ROCKCHIP_GPIO
+       bool "Rockchip GPIO driver"
+       depends on DM_GPIO
+       help
+         Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
+         a number of banks (different for each SoC type) each with 32 GPIOs.
+         The GPIOs for a device are defined in the device tree with one node
+         for each bank.
+
 config SANDBOX_GPIO
        bool "Enable sandbox GPIO driver"
        depends on SANDBOX && DM && DM_GPIO

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ba18594..c58aa4d 100644 (file)
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_MXC_GPIO)        += mxc_gpio.o
 obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
 obj-$(CONFIG_PCA953X)          += pca953x.o
 obj-$(CONFIG_PCA9698)          += pca9698.o
+obj-$(CONFIG_ROCKCHIP_GPIO)    += rk_gpio.o
 obj-$(CONFIG_S5P)              += s5p_gpio.o
 obj-$(CONFIG_SANDBOX_GPIO)     += sandbox.o
 obj-$(CONFIG_SPEAR_GPIO)       += spear_gpio.o

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
new file mode 100644 (file)
index 0000000..fbdf9f3
--- /dev/null
+++ b/drivers/gpio/rk_gpio.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ * Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dt-bindings/gpio/gpio.h>
+
+enum {
+       ROCKCHIP_GPIOS_PER_BANK         = 32,
+};
+
+#define OFFSET_TO_BIT(bit)     (1UL << (bit))
+
+struct rockchip_gpio_priv {
+       struct rockchip_gpio_regs *regs;
+       char name[2];
+};
+
+static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+       struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+       struct rockchip_gpio_regs *regs = priv->regs;
+
+       clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
+
+       return 0;
+}
+
+static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
+                                         int value)
+{
+       struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+       struct rockchip_gpio_regs *regs = priv->regs;
+       int mask = OFFSET_TO_BIT(offset);
+
+       clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
+       setbits_le32(&regs->swport_ddr, mask);
+
+       return 0;
+}
+
+static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+       struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+       struct rockchip_gpio_regs *regs = priv->regs;
+
+       return readl(&regs->ext_port) & OFFSET_TO_BIT(offset);
+}
+
+static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
+                                  int value)
+{
+       struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+       struct rockchip_gpio_regs *regs = priv->regs;
+       int mask = OFFSET_TO_BIT(offset);
+
+       clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
+
+       return 0;
+}
+
+static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+       return -ENOSYS;
+}
+
+static int rockchip_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+                           struct fdtdec_phandle_args *args)
+{
+       desc->offset = args->args[0];
+       desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+       return 0;
+}
+
+static int rockchip_gpio_probe(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+       struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+       char *end;
+       int bank;
+
+       priv->regs = (struct rockchip_gpio_regs *)dev_get_addr(dev);
+       uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
+       end = strrchr(dev->name, '@');
+       bank = trailing_strtoln(dev->name, end);
+       priv->name[0] = 'A' + bank;
+       uc_priv->bank_name = priv->name;
+
+       return 0;
+}
+
+static const struct dm_gpio_ops gpio_rockchip_ops = {
+       .direction_input        = rockchip_gpio_direction_input,
+       .direction_output       = rockchip_gpio_direction_output,
+       .get_value              = rockchip_gpio_get_value,
+       .set_value              = rockchip_gpio_set_value,
+       .get_function           = rockchip_gpio_get_function,
+       .xlate                  = rockchip_gpio_xlate,
+};
+
+static const struct udevice_id rockchip_gpio_ids[] = {
+       { .compatible = "rockchip,gpio-bank" },
+       { }
+};
+
+U_BOOT_DRIVER(gpio_rockchip) = {
+       .name   = "gpio_rockchip",
+       .id     = UCLASS_GPIO,
+       .of_match = rockchip_gpio_ids,
+       .ops    = &gpio_rockchip_ops,
+       .priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv),
+       .probe  = rockchip_gpio_probe,
+};