return DRM_FORMAT_MOD_LINEAR;
/* Default to tiled */
- return DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER;
+ return DRM_FORMAT_MOD_APPLE_TWIDDLED;
}
static struct pipe_resource *
pipe_resource_reference(&transfer->base.resource, resource);
*out_transfer = &transfer->base;
- if (rsrc->modifier == DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER) {
+ if (rsrc->modifier == DRM_FORMAT_MOD_APPLE_TWIDDLED) {
transfer->base.stride =
util_format_get_stride(resource->format, box->width);
/* Tiling will occur in software from a staging cpu buffer */
if ((transfer->usage & PIPE_MAP_WRITE) &&
- rsrc->modifier == DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER) {
+ rsrc->modifier == DRM_FORMAT_MOD_APPLE_TWIDDLED) {
assert(trans->map != NULL);
for (unsigned z = 0; z < transfer->box.depth; ++z) {
void *map = winsys->displaytarget_map(winsys, rsrc->dt, PIPE_USAGE_DEFAULT);
assert(map != NULL);
- if (rsrc->modifier == DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER) {
+ if (rsrc->modifier == DRM_FORMAT_MOD_APPLE_TWIDDLED) {
ail_detile(rsrc->bo->ptr.cpu, map, &rsrc->layout, 0, rsrc->dt_stride,
0, 0, rsrc->base.width0, rsrc->base.height0);
} else {
agx_translate_layout(uint64_t modifier)
{
switch (modifier) {
- case DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER:
+ case DRM_FORMAT_MOD_APPLE_TWIDDLED:
return AGX_LAYOUT_TWIDDLED;
case DRM_FORMAT_MOD_LINEAR:
return AGX_LAYOUT_LINEAR;
if (rsrc->modifier == DRM_FORMAT_MOD_LINEAR) {
cfg.stride = ail_get_linear_stride_B(&rsrc->layout, level) - 16;
} else {
- assert(rsrc->modifier == DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER);
+ assert(rsrc->modifier == DRM_FORMAT_MOD_APPLE_TWIDDLED);
cfg.stride = AGX_RT_STRIDE_TILED;
}
}
#ifndef DRM_FORMAT_MOD_LINEAR
#define DRM_FORMAT_MOD_LINEAR 1
#endif
-#define DRM_FORMAT_MOD_APPLE_64X64_MORTON_ORDER (2)
+#define DRM_FORMAT_MOD_APPLE_TWIDDLED (2)
struct agx_resource {
struct pipe_resource base;