Replace some structure-based batch preparation with plain OUT_BATCH.

OUT_BATCH is far more amenable to the upcoming relocations being done for TTM
support.

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index f88cbb2..da6b68c 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -535,9 +535,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
                                  GLshort w, GLshort h,
                                  GLenum logic_op)
 {
-   struct xy_setup_blit setup;
    struct xy_text_immediate_blit text;
    int dwords = ((src_size + 7) & ~7) / 4;
+   uint32_t opcode, br13;
 
    assert( logic_op - GL_CLEAR >= 0 );
    assert( logic_op - GL_CLEAR < 0x10 );
@@ -554,31 +554,6 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
        __FUNCTION__,
        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 
-   memset(&setup, 0, sizeof(setup));
-   
-   setup.br0.client = CLIENT_2D;
-   setup.br0.opcode = OPCODE_XY_SETUP_BLT;
-   setup.br0.write_alpha = (cpp == 4);
-   setup.br0.write_rgb = (cpp == 4);
-   setup.br0.dst_tiled = dst_tiled;
-   setup.br0.length = (sizeof(setup) / sizeof(int)) - 2;
-      
-   setup.br13.dest_pitch = dst_pitch;
-   setup.br13.rop = translate_raster_op(logic_op);
-   setup.br13.color_depth = (cpp == 4) ? BR13_8888 : BR13_565;
-   setup.br13.clipping_enable = 0;
-   setup.br13.mono_source_transparency = 1;
-
-   setup.dw2.clip_y1 = 0;
-   setup.dw2.clip_x1 = 0;
-   setup.dw3.clip_y2 = 100;
-   setup.dw3.clip_x2 = 100;
-
-   setup.dest_base_addr = bmBufferOffset(intel, dst_buffer) + dst_offset;
-   setup.background_color = 0;
-   setup.foreground_color = fg_color;
-   setup.pattern_base_addr = 0;
-
    memset(&text, 0, sizeof(text));
    text.dw0.client = CLIENT_2D;
    text.dw0.opcode = OPCODE_XY_TEXT_IMMEDIATE_BLT;
@@ -594,15 +569,33 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    text.dw2.dest_x2 = x + w;
 
    intel_batchbuffer_require_space( intel->batch,
-                                   sizeof(setup) + 
+                                   (8 * 4) +
                                    sizeof(text) + 
                                    dwords,
                                    INTEL_BATCH_NO_CLIPRECTS );
 
-   intel_batchbuffer_data( intel->batch,
-                          &setup,
-                          sizeof(setup),
-                          INTEL_BATCH_NO_CLIPRECTS );
+   opcode = XY_SETUP_BLT_CMD;
+   if (cpp == 4)
+      opcode |= XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
+   if (dst_tiled)
+      opcode |= XY_DST_TILED;
+
+   br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
+   if (cpp == 2)
+      br13 |= BR13_565 << 24;
+   else
+      br13 |= BR13_8888 << 24;
+
+   BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS);
+   OUT_BATCH(opcode);
+   OUT_BATCH(br13);
+   OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
+   OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
+   OUT_BATCH(bmBufferOffset(intel, dst_buffer) + dst_offset);
+   OUT_BATCH(0); /* bg */
+   OUT_BATCH(fg_color); /* fg */
+   OUT_BATCH(0); /* pattern base addr */
+   ADVANCE_BATCH();
 
    intel_batchbuffer_data( intel->batch,
                           &text,

diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
index 3c448b3..618afb6 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@ -32,7 +32,7 @@
 
 
 #define CMD_3D (0x3<<29)
-
+#define CMD_2D (0x2<<29)
 
 #define _3DPRIMITIVE         ((0x3<<29)|(0x1f<<24))
 #define PRIM_INDIRECT            (1<<23)
@@ -73,6 +73,8 @@
 #define BR00_OP_SRC_COPY_BLT 0x10C00000
 #define BR13_SOLID_PATTERN   0x80000000
 
+#define XY_SETUP_BLT_CMD               (CMD_2D | (1 << 22) | 6)
+
 #define XY_COLOR_BLT_CMD               ((2<<29)|(0x50<<22)|0x4)
 #define XY_COLOR_BLT_WRITE_ALPHA       (1<<21)
 #define XY_COLOR_BLT_WRITE_RGB         (1<<20)
@@ -81,6 +83,8 @@
 #define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
 #define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
 
+#define XY_BLT_WRITE_ALPHA     (1<<21)
+#define XY_BLT_WRITE_RGB       (1<<20)
 #define XY_SRC_TILED  (1<<15)
 #define XY_DST_TILED  (1<<11)