linux:dts:starfive: Add pm support for vout dts

Add pm support for vout dts
remove some useless port of vout dts

Signed-off-by: shengyang.chen<shengyang.chen@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 6a2b038..6ed31f8 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1544,6 +1544,13 @@
                        compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
                        ports = <&dc_out_dpi0>;
                        status = "disabled";
+                       clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
+                       <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
+                       <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
+                       clock-names = "hdmi_sysclk","hdmi_mclk","hdmi_bclk";
+                       resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
+                       reset-names = "hdmi_txrst";
+                       power-domains = <&pwrc JH7110_PD_VOUT>;
                };
 
                dssctrl: dssctrl@295B0000 {
@@ -1572,50 +1579,34 @@
                              <0x0 0x17030000 0x0 0x1000>;
                        interrupts = <95>;
                        status = "disabled";
-                       clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
-                                <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
-                                <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
-                                <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
-                                <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
-                                <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
-                                <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
-                                <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
-                                <&clkgen JH7110_VOUT_SRC>,
-                                <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
-                                <&clkgen JH7110_AHB1>,
-                                <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
-                                <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
-                                <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
-                                <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
-                                <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
-                                <&clkvout JH7110_U0_DC8200_CLK_AXI>,
-                                <&clkvout JH7110_U0_DC8200_CLK_CORE>,
-                                <&clkvout JH7110_U0_DC8200_CLK_AHB>,
-                                <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
-                                <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
-                                <&hdmitx0_pixelclk>,
-                                <&clkvout JH7110_DC8200_PIX0>,
-                                <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
-                                <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
-                       clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
-                                       "noc_disp","noc_isp","noc_stg","vout_src",
-                                       "top_vout_axi","ahb1","top_vout_ahb",
-                                       "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
-                                       "axi_clk","core_clk","vout_ahb",
-                                       "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
-                                       "dc8200_pix0_out","dc8200_pix1_out";
+                       clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
+                       <&clkgen JH7110_VOUT_SRC>,
+                       <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+                       <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
+                       <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
+                       <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
+                       <&clkvout JH7110_U0_DC8200_CLK_AXI>,
+                       <&clkvout JH7110_U0_DC8200_CLK_CORE>,
+                       <&clkvout JH7110_U0_DC8200_CLK_AHB>,
+                       <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+                       <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
+                       <&hdmitx0_pixelclk>,
+                       <&clkvout JH7110_DC8200_PIX0>,
+                       <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
+                       <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
+                       clock-names = "noc_disp","vout_src",
+                          "top_vout_axi","top_vout_ahb",
+                          "pix_clk","vout_pix1",
+                          "axi_clk","core_clk","vout_ahb",
+                          "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
+                          "dc8200_pix0_out","dc8200_pix1_out";
                        resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
                                 <&rstgen RSTN_U0_DC8200_AXI>,
                                 <&rstgen RSTN_U0_DC8200_AHB>,
                                 <&rstgen RSTN_U0_DC8200_CORE>,
-                                <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
-                                <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
-                                <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
-                                <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
-                                <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
+                                <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
                        reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
-                                       "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
-                                       "rst_noc_disp","rst_noc_stg";
+                                       "rst_noc_disp";
                        power-domains = <&pwrc JH7110_PD_VOUT>;
                };
 
@@ -1687,7 +1678,7 @@
                                 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
                                 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
                                 <&hdmitx0_pixelclk>;
-                       clock-names = "sysclk", "mclk", "bclk", "pclk";
+                       clock-names = "sysclk", "mclk","bclk","pclk";
                        resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
                        reset-names = "hdmi_tx";
                        #sound-dai-cells = <0>;