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drm/i915/gvt: fix an error for one register
author
Zhao Yan
<yan.y.zhao@intel.com>
Tue, 28 Feb 2017 07:41:03 +0000
(15:41 +0800)
committer
Zhenyu Wang
<zhenyuw@linux.intel.com>
Wed, 1 Mar 2017 02:12:36 +0000
(10:12 +0800)
register 0x20e0 should be mode register
v2: rebased to latest code base
Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/handlers.c
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diff --git
a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index
ef17c38
..
548aedf
100644
(file)
--- a/
drivers/gpu/drm/i915/gvt/handlers.c
+++ b/
drivers/gpu/drm/i915/gvt/handlers.c
@@
-2749,7
+2749,7
@@
static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);
MMIO_D(0xd08, D_SKL);
- MMIO_D
(0x20e0, D_SK
L);
+ MMIO_D
FH(0x20e0, D_SKL, F_MODE_MASK, NULL, NUL
L);
MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
/* TRTT */