* gas/testsuite/gas/arm/thumb-eabi.d: Add case for divided syntax encoding of movs.
authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>
Mon, 7 Jun 2010 10:43:52 +0000 (10:43 +0000)
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>
Mon, 7 Jun 2010 10:43:52 +0000 (10:43 +0000)
* gas/testsuite/gas/arm/thumb.d: Likewise.
* gas/testsuite/gas/arm/thumb.s: Likewise.
* gas/testsuite/gas/arm/thumb2_it.d: Update for change in lsls/movs disassembly.
* gas/testsuite/gas/arm/thumb2_it_auto.d: Liekwise.
* gas/testsuite/gas/arm/thumb32.d: Likewise.
* ld/testsuite/ld-arm/arm-call.d: Handle change in lsls/movs disassembly.
* ld/testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise.
* ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d: Likewise.
* ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d: Likewise.
* ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d: Likewise.
* ld/testsuite/ld-arm/farcall-thumb-thumb-m.d: Likewise.
* ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise.
* ld/testsuite/ld-arm/farcall-thumb-thumb.d: Likewise.
* ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d: Likewise.
* ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d: Likewise.
* ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d: Likewise.
* ld/testsuite/ld-arm/thumb2-bl-bad.d: Likewise.
* opcodes/arm-dis.c (thumb-opcodes): Add disassembly for movs.

22 files changed:
gas/testsuite/ChangeLog
gas/testsuite/gas/arm/thumb-eabi.d
gas/testsuite/gas/arm/thumb.d
gas/testsuite/gas/arm/thumb.s
gas/testsuite/gas/arm/thumb2_it.d
gas/testsuite/gas/arm/thumb2_it_auto.d
gas/testsuite/gas/arm/thumb32.d
ld/testsuite/ChangeLog
ld/testsuite/ld-arm/arm-call.d
ld/testsuite/ld-arm/farcall-thumb-arm-short.d
ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d
ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d
ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d
ld/testsuite/ld-arm/farcall-thumb-thumb-m.d
ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d
ld/testsuite/ld-arm/farcall-thumb-thumb.d
ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d
ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d
ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d
ld/testsuite/ld-arm/thumb2-bl-bad.d
opcodes/ChangeLog
opcodes/arm-dis.c

index b488019..7701f2a 100644 (file)
@@ -1,3 +1,11 @@
+2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+       * gas/arm/thumb-eabi.d: Add case for divided syntax encoding of movs.
+       * gas/arm/thumb.d: Likewise.
+       * gas/arm/thumb.s: Likewise.
+       * gas/arm/thumb2_it.d: Update for change in lsls/movs disassembly.
+       * gas/arm/thumb2_it_auto.d: Liekwise.
+       * gas/arm/thumb32.d: Likewise.
+
 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
        * gas/arm/thumb2_it_auto.d: Update for change in movs encoding.
index 188a2e2..9fd77d1 100644 (file)
@@ -10,9 +10,9 @@ Disassembly of section \.text:
 0+000 <[^>]+> 00ca             lsls    r2, r1, #3
 0+002 <[^>]+> 0fe3             lsrs    r3, r4, #31
 0+004 <[^>]+> 1147             asrs    r7, r0, #5
-0+006 <[^>]+> 0011             lsls    r1, r2, #0
-0+008 <[^>]+> 0023             lsls    r3, r4, #0
-0+00a <[^>]+> 002c             lsls    r4, r5, #0
+0+006 <[^>]+> 0011             movs    r1, r2
+0+008 <[^>]+> 0023             movs    r3, r4
+0+00a <[^>]+> 002c             movs    r4, r5
 0+00c <[^>]+> 083e             lsrs    r6, r7, #32
 0+00e <[^>]+> 1008             asrs    r0, r1, #32
 0+010 <[^>]+> 18d1             adds    r1, r2, r3
@@ -161,5 +161,5 @@ Disassembly of section \.text:
 0+93e <[^>]+> 4801             ldr     r0, \[pc, #4\]  ; \(0+944 <[^>]+>\)
 0+940 <[^>]+> 4801             ldr     r0, \[pc, #4\]  ; \(0+948 <[^>]+>\)
 0+942 <[^>]+> 4801             ldr     r0, \[pc, #4\]  ; \(0+948 <[^>]+>\)
-0+944 <[^>]+> 46c0             nop                     ; \(mov r8, r8\)
+0+944 <[^>]+> 1c08             adds    r0, r1, #0
 0+946 <[^>]+> 46c0             nop                     ; \(mov r8, r8\)
index 7ee5582..6d88508 100644 (file)
@@ -11,9 +11,9 @@ Disassembly of section \.text:
 0+000 <[^>]+> 00ca             lsls    r2, r1, #3
 0+002 <[^>]+> 0fe3             lsrs    r3, r4, #31
 0+004 <[^>]+> 1147             asrs    r7, r0, #5
-0+006 <[^>]+> 0011             lsls    r1, r2, #0
-0+008 <[^>]+> 0023             lsls    r3, r4, #0
-0+00a <[^>]+> 002c             lsls    r4, r5, #0
+0+006 <[^>]+> 0011             movs    r1, r2
+0+008 <[^>]+> 0023             movs    r3, r4
+0+00a <[^>]+> 002c             movs    r4, r5
 0+00c <[^>]+> 083e             lsrs    r6, r7, #32
 0+00e <[^>]+> 1008             asrs    r0, r1, #32
 0+010 <[^>]+> 18d1             adds    r1, r2, r3
@@ -161,5 +161,5 @@ Disassembly of section \.text:
 0+93e <[^>]+> 4801             ldr     r0, \[pc, #4\]  ; \(0+944 <[^>]+>\)
 0+940 <[^>]+> 4801             ldr     r0, \[pc, #4\]  ; \(0+948 <[^>]+>\)
 0+942 <[^>]+> 4801             ldr     r0, \[pc, #4\]  ; \(0+948 <[^>]+>\)
-0+944 <[^>]+> 46c0             nop                     ; \(mov r8, r8\)
+0+944 <[^>]+> 1c08             adds    r0, r1, #0
 0+946 <[^>]+> 46c0             nop                     ; \(mov r8, r8\)
index d1e4339..a044bdf 100644 (file)
@@ -198,5 +198,6 @@ forwardonly:
        ldr     r0, [pc, #4]
        ldr     r0, [pc, #4]
 .target:
-       nop     @ pad for a.out
+baz:
+       mov     r0, r1
        nop
index b55bc67..b02659f 100644 (file)
@@ -45,7 +45,7 @@ Disassembly of section .text:
 0+062 <[^>]+> bf08             it      eq
 0+064 <[^>]+> 4640             moveq   r0, r8
 0+066 <[^>]+> 4608             mov     r0, r1
-0+068 <[^>]+> 0008             lsls    r0, r1, #0
+0+068 <[^>]+> 0008             movs    r0, r1
 0+06a <[^>]+> ea5f 0008        movs.w  r0, r8
 0+06e <[^>]+> bf01             itttt   eq
 0+070 <[^>]+> 43c8             mvneq   r0, r1
index 91d82ca..03ad87c 100644 (file)
@@ -45,7 +45,7 @@ Disassembly of section .text:
 0+062 <[^>]+> bf08             it      eq
 0+064 <[^>]+> 4640             moveq   r0, r8
 0+066 <[^>]+> 4608             mov     r0, r1
-0+068 <[^>]+> 0008             lsls    r0, r1, #0
+0+068 <[^>]+> 0008             movs    r0, r1
 0+06a <[^>]+> ea5f 0008        movs.w  r0, r8
 0+06e <[^>]+> bf01             itttt   eq
 0+070 <[^>]+> 43c8             mvneq   r0, r1
index 31278d8..2499f73 100644 (file)
@@ -618,9 +618,9 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> eb10 0f09   cmn\.w  r0, r9
 0[0-9a-f]+ <[^>]+> f110 0f81   cmn\.w  r0, #129        ; 0x81
 0[0-9a-f]+ <[^>]+> f115 0f81   cmn\.w  r5, #129        ; 0x81
-0[0-9a-f]+ <[^>]+> 0000        lsls    r0, r0, #0
+0[0-9a-f]+ <[^>]+> 0000        movs    r0, r0
 0[0-9a-f]+ <[^>]+> 4600        mov     r0, r0
-0[0-9a-f]+ <[^>]+> 0005        lsls    r5, r0, #0
+0[0-9a-f]+ <[^>]+> 0005        movs    r5, r0
 0[0-9a-f]+ <[^>]+> 4628        mov     r0, r5
 0[0-9a-f]+ <[^>]+> ea4f 4065   mov\.w  r0, r5, asr #17
 0[0-9a-f]+ <[^>]+> ea4f 0000   mov\.w  r0, r0
index a59ad4a..162f166 100644 (file)
@@ -1,3 +1,18 @@
+2010-06-07  Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+       * ld-arm/arm-call.d: Handle change in lsls/movs disassembly.
+       * ld-arm/farcall-thumb-arm-short.d: Likewise.
+       * ld-arm/farcall-thumb-thumb-blx-pic-veneer.d: Likewise.
+       * ld-arm/farcall-thumb-thumb-blx.d: Likewise.
+       * ld-arm/farcall-thumb-thumb-m-pic-veneer.d: Likewise.
+       * ld-arm/farcall-thumb-thumb-m.d: Likewise.
+       * ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise.
+       * ld-arm/farcall-thumb-thumb.d: Likewise.
+       * ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d: Likewise.
+       * ld-arm/thumb2-bl-as-thumb1-bad.d: Likewise.
+       * ld-arm/thumb2-bl-bad-noeabi.d: Likewise.
+       * ld-arm/thumb2-bl-bad.d: Likewise.
+
 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/11628
index fa452ab..a320743 100644 (file)
@@ -46,7 +46,7 @@ Disassembly of section .text:
     8050:      f7ff fff1       bl      8036 <t3>
     8054:      f7ff efd4       blx     8000 <_start>
     8058:      f7ff efd2       blx     8000 <_start>
-    805c:      0000            lsls    r0, r0, #0
+    805c:      0000            movs    r0, r0
        ...
 
 00008060 <__t1_from_arm>:
index f4caf87..4e19039 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 f802       bl      1008 <__bar_from_thumb>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        \.\.\.
 
 00001008 <__bar_from_thumb>:
index 86c0ca0..27b208e 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 e802       blx     1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        \.\.\.
 
 00001008 <__bar_veneer>:
index 5e9ac5a..7998746 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 e802       blx     1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        \.\.\.
 
 00001008 <__bar_veneer>:
index 79e6449..974c1e9 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 f802       bl      1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        ...
 
 00001008 <__bar_veneer>:
index 84782b8..e63b3f8 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 f802       bl      1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        \.\.\.
 
 00001008 <__bar_veneer>:
index 8c2cddf..8b14599 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 f802       bl      1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        ...
 
 00001008 <__bar_veneer>:
index 8ea41c7..ffbc6df 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 f802       bl      1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        \.\.\.
 
 00001008 <__bar_veneer>:
index 540c452..8872909 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 f802       bl      1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        ...
 
 00001008 <__bar_veneer>:
index 04eb991..6b47810 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 e802       blx     1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        \.\.\.
 
 00001008 <__bar_veneer>:
index 540c452..8872909 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 f802       bl      1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        ...
 
 00001008 <__bar_veneer>:
index 89c7a55..d78e451 100644 (file)
@@ -4,7 +4,7 @@ Disassembly of section .text:
 
 00001000 <_start>:
     1000:      f000 e802       blx     1008 <__bar_veneer>
-    1004:      0000            lsls    r0, r0, #0
+    1004:      0000            movs    r0, r0
        \.\.\.
 
 00001008 <__bar_veneer>:
index 9ec2d50..3055bc0 100644 (file)
@@ -1,3 +1,7 @@
+2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+       * arm-dis.c (thumb-opcodes): Add disassembly for movs.
+
 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
        * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon 
index 3763c1e..174de5a 100644 (file)
@@ -1249,6 +1249,7 @@ static const struct opcode16 thumb_opcodes[] =
   {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
   {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
   /* format 1 */
+  {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
   {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
   {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
   {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},