osd: rdma overflow handling
authorpengcheng chen <pengcheng.chen@amlogic.com>
Sat, 19 May 2018 11:06:03 +0000 (19:06 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Tue, 22 May 2018 08:27:29 +0000 (01:27 -0700)
PD#165381: osd: rdma overflow handling

Change-Id: Ic82a7d03ef3f985720e0c84bf9c65f5dee9324a9
Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>
drivers/amlogic/media/common/rdma/rdma_mgr.c
drivers/amlogic/media/osd/osd_rdma.c
drivers/amlogic/media/osd/osd_rdma.h

index e965ce0..bc562a8 100644 (file)
@@ -62,7 +62,7 @@ static int debug_flag;
 /* burst size 0=16; 1=24; 2=32; 3=48.*/
 static int ctrl_ahb_rd_burst_size = 3;
 static int ctrl_ahb_wr_burst_size = 3;
-static int rdma_watchdog = 10;
+static int rdma_watchdog = 20;
 static int reset_count;
 static int rdma_watchdog_count;
 static int rdma_force_reset = -1;
index cefd785..8e9c817 100644 (file)
@@ -81,7 +81,9 @@ static unsigned int rdma_recovery_count;
 #ifdef OSD_RDMA_ISR
 static unsigned int second_rdma_irq;
 #endif
+static unsigned int vsync_irq_count;
 
+static bool osd_rdma_done;
 static int osd_rdma_handle = -1;
 static struct rdma_table_item *rdma_temp_tbl;
 
@@ -216,12 +218,41 @@ static int update_table_item(u32 addr, u32 val, u8 irq_mode)
        struct rdma_table_item request_item;
        int reject1 = 0, reject2 = 0, ret = 0;
        u32 paddr;
+       static int pace_logging;
 
        if ((item_count > 500) || rdma_reset_tigger_flag) {
+               int i;
+               struct rdma_table_item reset_item[2] = {
+                       {
+                               .addr = OSD_RDMA_FLAG_REG,
+                               .val = OSD_RDMA_STATUS_MARK_TBL_RST,
+                       },
+                       {
+                               .addr = OSD_RDMA_FLAG_REG,
+                               .val = OSD_RDMA_STATUS_MARK_TBL_DONE,
+                       }
+               };
+
                /* rdma table is full */
-               /* pr_info("update_table_item overflow!\n"); */
+               if (!(pace_logging++ % 50))
+                       pr_info("update_table_item overflow!vsync_cnt=%d, rdma_cnt=%d\n",
+                               vsync_irq_count, rdma_irq_count);
+               /* update rdma table */
+               for (i = 1; i < item_count - 1; i++)
+                       osd_reg_write(rdma_table[i].addr, rdma_table[i].val);
+
+               osd_reg_write(addr, val);
+               update_recovery_item(addr, val);
+
+               item_count = 2;
+               osd_rdma_mem_cpy(rdma_table, &reset_item[0], 8);
+               osd_rdma_mem_cpy(&rdma_table[item_count - 1],
+                       &reset_item[1], 8);
+               osd_reg_write(END_ADDR,
+                       (table_paddr + item_count * 8 - 1));
                return -1;
        }
+
        /* pr_debug("%02dth, ctrl: 0x%x, status: 0x%x, auto:0x%x, flag:0x%x\n",
         *      item_count, osd_reg_read(RDMA_CTRL),
         *      osd_reg_read(RDMA_STATUS),
@@ -981,6 +1012,7 @@ static void osd_rdma_irq(void *arg)
        osd_update_3d_mode();
        osd_hw_reset();
        rdma_irq_count++;
+       osd_rdma_done = true;
        {
                /*This is a memory barrier*/
                wmb();
@@ -1067,6 +1099,14 @@ void osd_rdma_interrupt_done_clear(void)
 {
        u32 rdma_status;
 
+       vsync_irq_count++;
+
+       if (osd_rdma_done)
+               rdma_watchdog_setting(0);
+       else
+               rdma_watchdog_setting(1);
+       osd_rdma_done = false;
+
        if (rdma_reset_tigger_flag) {
                rdma_status =
                        osd_reg_read(RDMA_STATUS);
@@ -1409,3 +1449,6 @@ module_param(rdma_recovery_count, uint, 0664);
 
 MODULE_PARM_DESC(rdma_hdr_delay, "\n rdma_hdr_delay\n");
 module_param(rdma_hdr_delay, uint, 0664);
+
+MODULE_PARM_DESC(vsync_irq_count, "\n vsync_irq_count\n");
+module_param(vsync_irq_count, uint, 0664);
index b489591..4e78e4f 100644 (file)
@@ -22,6 +22,8 @@
 #include "osd_io.h"
 #include "osd_reg.h"
 
+extern int rdma_watchdog_setting(int flag);
+
 struct rdma_table_item {
        u32 addr;
        u32 val;