armv7-r/mpu: clean up inconsistent indentations

Fix inconsistent indentation in mpu.h for better readability. This
commit does not introduce any functional differences.

Change-Id: Ic9209c9e187c2a1153bc9c058f29c776c4ed6109
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>

diff --git a/os/arch/arm/src/armv7-r/mpu.h b/os/arch/arm/src/armv7-r/mpu.h
index 9b72b9e..5610096 100644 (file)
--- a/os/arch/arm/src/armv7-r/mpu.h
+++ b/os/arch/arm/src/armv7-r/mpu.h
@@ -78,61 +78,61 @@
 
 /* MPU Type Register Bit Definitions */
 
-#define MPUIR_SEPARATE           (1 << 0)      /* Bit 0: 0:unified or 1:separate memory maps */
-#define MPUIR_DREGION_SHIFT      (8)   /* Bits 8-15: Number MPU data regions */
-#define MPUIR_DREGION_MASK       (0xff << MPUIR_DREGION_SHIFT)
-#define MPUIR_IREGION_SHIFT      (16)  /* Bits 16-23: Number MPU instruction regions */
-#define MPUIR_IREGION_MASK       (0xff << MPUIR_IREGION_SHIFT)
+#define MPUIR_SEPARATE         (1 << 0) /* Bit 0: 0:unified or 1:separate memory maps */
+#define MPUIR_DREGION_SHIFT    (8)      /* Bits 8-15: Number MPU data regions */
+#define MPUIR_DREGION_MASK     (0xff << MPUIR_DREGION_SHIFT)
+#define MPUIR_IREGION_SHIFT    (16)     /* Bits 16-23: Number MPU instruction regions */
+#define MPUIR_IREGION_MASK     (0xff << MPUIR_IREGION_SHIFT)
 
 /* Region Base Address Register Definitions */
 
-#define MPU_RBAR_ADDR_MASK            0xfffffffe
+#define MPU_RBAR_ADDR_MASK     0xfffffffe
 
 /* Region Size and Enable Register */
 
-#define MPU_RASR_ENABLE          (1 << 0)      /* Bit 0: Region enable */
-#define MPU_RASR_RSIZE_SHIFT     (1)   /* Bits 1-5: Size of the MPU protection region */
-#define MPU_RASR_RSIZE_MASK      (31 << MPU_RASR_RSIZE_SHIFT)
-#define MPU_RASR_RSIZE_LOG2(n) ((n-1) << MPU_RASR_RSIZE_SHIFT)
-
-#define MPU_RASR_SRD_SHIFT       (8)   /* Bits 8-15: Subregion disable */
-#define MPU_RASR_SRD_MASK        (0xff << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_0         (0x01 << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_1         (0x02 << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_2         (0x04 << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_3         (0x08 << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_4         (0x10 << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_5         (0x20 << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_6         (0x40 << MPU_RASR_SRD_SHIFT)
-#define MPU_RASR_SRD_7         (0x80 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_ENABLE                (1 << 0) /* Bit 0: Region enable */
+#define MPU_RASR_RSIZE_SHIFT   (1)      /* Bits 1-5: Size of the MPU protection region */
+#define MPU_RASR_RSIZE_MASK    (31 << MPU_RASR_RSIZE_SHIFT)
+#define MPU_RASR_RSIZE_LOG2(n) ((n-1) << MPU_RASR_RSIZE_SHIFT)
+
+#define MPU_RASR_SRD_SHIFT     (8)      /* Bits 8-15: Subregion disable */
+#define MPU_RASR_SRD_MASK      (0xff << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_0         (0x01 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_1         (0x02 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_2         (0x04 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_3         (0x08 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_4         (0x10 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_5         (0x20 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_6         (0x40 << MPU_RASR_SRD_SHIFT)
+#define MPU_RASR_SRD_7         (0x80 << MPU_RASR_SRD_SHIFT)
 
 /* Region Access Control Register */
 
-#define MPU_RACR_B               (1 << 0)      /* Bit 0: Bufferable */
-#define MPU_RACR_C               (1 << 1)      /* Bit 1: Cacheable */
-#define MPU_RACR_S               (1 << 2)      /* Bit 2: Shareable */
-#define MPU_RACR_TEX_SHIFT       (3)   /* Bits 0-2: Memory attributes (with C and B) */
-#define MPU_RACR_TEX_MASK        (7 << MPU_RACR_TEX_SHIFT)
-#define MPU_RACR_TEX(n)        ((uint32_t)(n) << MPU_RACR_TEX_SHIFT)
-#define MPU_RACR_AP_SHIFT        (8)   /* Bits 8-10: Access permission */
-#define MPU_RACR_AP_MASK         (7 << MPU_RACR_AP_SHIFT)
-#define MPU_RACR_AP_NONO       (0 << MPU_RACR_AP_SHIFT)        /* PL0:None PL1:None */
-#define MPU_RACR_AP_RWNO       (1 << MPU_RACR_AP_SHIFT)        /* PL0:RW   PL1:None */
-#define MPU_RACR_AP_RWRO       (2 << MPU_RACR_AP_SHIFT)        /* PL0:RW   PL1:RO   */
-#define MPU_RACR_AP_RWRW       (3 << MPU_RACR_AP_SHIFT)        /* PL0:RW   PL1:RW   */
-#define MPU_RACR_AP_RONO       (5 << MPU_RACR_AP_SHIFT)        /* PL0:RO   PL1:None */
-#define MPU_RACR_AP_RORO       (6 << MPU_RACR_AP_SHIFT)        /* PL0:RO   PL1:RO   */
-#define MPU_RACR_XN              (1 << 12)     /* Bit 12: Instruction access disable */
+#define MPU_RACR_B             (1 << 0) /* Bit 0: Bufferable */
+#define MPU_RACR_C             (1 << 1) /* Bit 1: Cacheable */
+#define MPU_RACR_S             (1 << 2) /* Bit 2: Shareable */
+#define MPU_RACR_TEX_SHIFT     (3)      /* Bits 0-2: Memory attributes (with C and B) */
+#define MPU_RACR_TEX_MASK      (7 << MPU_RACR_TEX_SHIFT)
+#define MPU_RACR_TEX(n)                ((uint32_t)(n) << MPU_RACR_TEX_SHIFT)
+#define MPU_RACR_AP_SHIFT      (8)      /* Bits 8-10: Access permission */
+#define MPU_RACR_AP_MASK       (7 << MPU_RACR_AP_SHIFT)
+#define MPU_RACR_AP_NONO       (0 << MPU_RACR_AP_SHIFT) /* PL0:None PL1:None */
+#define MPU_RACR_AP_RWNO       (1 << MPU_RACR_AP_SHIFT) /* PL0:RW   PL1:None */
+#define MPU_RACR_AP_RWRO       (2 << MPU_RACR_AP_SHIFT) /* PL0:RW   PL1:RO   */
+#define MPU_RACR_AP_RWRW       (3 << MPU_RACR_AP_SHIFT) /* PL0:RW   PL1:RW   */
+#define MPU_RACR_AP_RONO       (5 << MPU_RACR_AP_SHIFT) /* PL0:RO   PL1:None */
+#define MPU_RACR_AP_RORO       (6 << MPU_RACR_AP_SHIFT) /* PL0:RO   PL1:RO   */
+#define MPU_RACR_XN            (1 << 12) /* Bit 12: Instruction access disable */
 
 /* MPU Region Number Register */
 
 #if defined(CONFIG_ARMV7M_MPU_NREGIONS)
 #if CONFIG_ARMV7M_MPU_NREGIONS <= 8
-#define MPU_RGNR_MASK        (0x00000007)
+#define MPU_RGNR_MASK  (0x00000007)
 #elif CONFIG_ARMV7M_MPU_NREGIONS <= 16
-#define MPU_RGNR_MASK        (0x0000000f)
+#define MPU_RGNR_MASK  (0x0000000f)
 #elif CONFIG_ARMV7M_MPU_NREGIONS <= 32
-#define MPU_RGNR_MASK        (0x0000001f)
+#define MPU_RGNR_MASK  (0x0000001f)
 #else
 #error "FIXME: Unsupported number of MPU regions"
 #endif
@@ -472,9 +472,15 @@ static inline void mpu_show_regioninfo(void)
                base = get_mpu_region_base();
                size = get_mpu_region_size();
                attr = get_mpu_region_access_ctrl();
-               lldbg("%8d\t\t%8X\t%8X\t%8d\t%8X\n", (regval & MPU_RGNR_MASK), (base & MPU_RBAR_ADDR_MASK), (size ? (1 << (((size & MPU_RASR_RSIZE_MASK) >> MPU_RASR_RSIZE_SHIFT) + 1)) : 0), (size & MPU_RASR_ENABLE) ? 1 : 0, attr);
+               lldbg("%8d\t\t%8X\t%8X\t%8d\t%8X\n",
+                       regval & MPU_RGNR_MASK,
+                       base & MPU_RBAR_ADDR_MASK,
+                       size ? (1 << (((size & MPU_RASR_RSIZE_MASK) >> MPU_RASR_RSIZE_SHIFT) + 1)) : 0,
+                       size & MPU_RASR_ENABLE ? 1 : 0,
+                       attr);
        }
        lldbg("*****************************************************************************\n");
+
        /* restore the previous region */
        mpu_set_rgnr(temp);
 #endif
@@ -523,30 +529,27 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size, int reg
        uint8_t subregions;
 
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
-       /* Select the region */
 
+       /* Select the region */
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
-       regval =                                        /* Not Cacheable  */
-               /* Not Bufferable */
-               MPU_RACR_S |                    /* Shareable      */
-               MPU_RACR_AP_RWNO;               /* P:RW   U:None  */
+       regval =                                          /* Not Cacheable  */
+                                                         /* Not Bufferable */
+               MPU_RACR_S                              | /* Shareable      */
+               MPU_RACR_AP_RWNO;                         /* P:RW   U:None  */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region  */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size    */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions    */
+       regval = MPU_RASR_ENABLE                        | /* Enable region  */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size    */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 #endif
@@ -568,28 +571,25 @@ static inline void mpu_user_flash(uintptr_t base, size_t size, int region)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
 
-       regval =                                        /* Not Cacheable  */
-               MPU_RACR_C |                    /* Cacheable     */
-               MPU_RACR_AP_RORO;               /* P:RO   U:RO   */
+       regval =                                          /* Not Cacheable */
+               MPU_RACR_C                              | /* Cacheable     */
+               MPU_RACR_AP_RORO;                         /* P:RO   U:RO   */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -610,32 +610,28 @@ static inline void mpu_priv_noncache(uintptr_t base, size_t size, int region)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
        /* inner/outer non-cache : TEX(4), C(0), B(0), S(1) */
-
-       regval =                                        /* Not Cacheable  */
-               /* Not Bufferable */
-               MPU_RACR_S |                    /* Shareable      */
-               MPU_RACR_TEX(4) |               /* TEX */
-               MPU_RACR_AP_RWRW |              /* P:RO   U:None */
-               MPU_RACR_XN;                    /* Instruction access disable */
+       regval =                                          /* Not Cacheable  */
+                                                         /* Not Bufferable */
+               MPU_RACR_S                              | /* Shareable      */
+               MPU_RACR_TEX(4)                         | /* TEX */
+               MPU_RACR_AP_RWRW                        | /* P:RO   U:None  */
+               MPU_RACR_XN;                              /* Instruction access disable */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -656,27 +652,23 @@ static inline void mpu_priv_flash(uintptr_t base, size_t size, int region)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
-       regval = MPU_RACR_C |           /* Cacheable     */
-                        MPU_RACR_AP_RONO;              /* P:RO   U:None */
+       regval = MPU_RACR_C                             | /* Cacheable     */
+                MPU_RACR_AP_RONO;                        /* P:RO   U:None */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -697,28 +689,24 @@ static inline void mpu_user_intsram(uintptr_t base, size_t size, int region)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
-       regval = MPU_RACR_S |           /* Shareable     */
-                        MPU_RACR_C |                   /* Cacheable     */
-                        MPU_RACR_AP_RWRW;              /* P:RW   U:RW   */
+       regval = MPU_RACR_S                             | /* Shareable     */
+                MPU_RACR_C                             | /* Cacheable     */
+                MPU_RACR_AP_RWRW;                        /* P:RW   U:RW   */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -740,28 +728,24 @@ static inline void mpu_priv_intsram(uintptr_t base, size_t size)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
-       regval = MPU_RACR_S |           /* Shareable     */
-                        MPU_RACR_C |                   /* Cacheable     */
-                        MPU_RACR_AP_RWNO;              /* P:RW   U:None */
+       regval = MPU_RACR_S                             | /* Shareable     */
+                MPU_RACR_C                             | /* Cacheable     */
+                MPU_RACR_AP_RWNO;                        /* P:RW   U:None */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -782,29 +766,25 @@ static inline void mpu_user_extsram(uintptr_t base, size_t size, int region)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
-       regval = MPU_RACR_S |           /* Shareable     */
-                        MPU_RACR_C |                   /* Cacheable     */
-                        MPU_RACR_B |                   /* Bufferable    */
-                        MPU_RACR_AP_RWRW;              /* P:RW   U:RW   */
+       regval = MPU_RACR_S                             | /* Shareable     */
+                MPU_RACR_C                             | /* Cacheable     */
+                MPU_RACR_B                             | /* Bufferable    */
+                MPU_RACR_AP_RWRW;                        /* P:RW   U:RW   */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -826,29 +806,25 @@ static inline void mpu_priv_extsram(uintptr_t base, size_t size)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
-       regval = MPU_RACR_S |           /* Shareable     */
-                        MPU_RACR_C |                   /* Cacheable     */
-                        MPU_RACR_B |                   /* Bufferable    */
-                        MPU_RACR_AP_RWNO;              /* P:RW   U:None */
+       regval = MPU_RACR_S                             | /* Shareable     */
+                MPU_RACR_C                             | /* Cacheable     */
+                MPU_RACR_B                             | /* Bufferable    */
+                MPU_RACR_AP_RWNO;                        /* P:RW   U:None */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -870,29 +846,25 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
 
        /* Select the region */
-
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* Then configure the region */
-
-       regval = MPU_RACR_S |           /* Shareable     */
-                        MPU_RACR_B |                   /* Bufferable    */
-                        MPU_RACR_AP_RWNO |             /* P:RW   U:None */
-                        MPU_RACR_XN;                   /* Instruction access disable */
+       regval = MPU_RACR_S                             | /* Shareable     */
+                MPU_RACR_B                             | /* Bufferable    */
+                MPU_RACR_AP_RWNO                       | /* P:RW   U:None */
+                MPU_RACR_XN;                             /* Instruction access disable */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -917,30 +889,26 @@ static inline void mpu_priv_intsram_wb(uintptr_t base, size_t size, int region)
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
        /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) */
-
-       regval =                                        /* Not Cacheable  */
-               MPU_RACR_B |                    /* Not Bufferable */
+       regval =                                          /* Not Cacheable  */
+                MPU_RACR_B                             | /* Not Bufferable */
 #if !defined(CONFIG_ARCH_CORTEXR4)
-               MPU_RACR_S |                    /* Shareable      */
+                MPU_RACR_S                             | /* Shareable      */
 #endif
-               MPU_RACR_TEX(5) |               /* TEX */
-               MPU_RACR_AP_RWNO;               /* P:RW   U:NO */
+                MPU_RACR_TEX(5)                        | /* TEX */
+                MPU_RACR_AP_RWNO;                        /* P:RW   U:NO */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -951,34 +919,31 @@ static inline void mpu_user_intsram_ro(uintptr_t base, size_t size, int region)
        uint8_t subregions;
 
        DEBUGASSERT(region < (uintptr_t)CONFIG_ARMV7M_MPU_NREGIONS);
+
        /* Select the region */
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
        /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) except cortex-r4(S(0)) */
-
-       regval =                                        /* Not Cacheable  */
-               MPU_RACR_B |                    /* Not Bufferable */
+       regval =                                          /* Not Cacheable  */
+                MPU_RACR_B                             | /* Not Bufferable */
 #if !defined(CONFIG_ARCH_CORTEXR4)
-               MPU_RACR_S |                    /* Shareable      */
+                MPU_RACR_S                             | /* Shareable      */
 #endif
-               MPU_RACR_TEX(5) |               /* TEX */
-               MPU_RACR_AP_RWNO;               /* P:RW   U:NO */
+                MPU_RACR_TEX(5)                        | /* TEX */
+                MPU_RACR_AP_RWNO;                        /* P:RW   U:NO */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -1003,30 +968,26 @@ static inline void mpu_user_intsram_wb(uintptr_t base, size_t size, int region)
        mpu_set_rgnr(region);
 
        /* Select the region base address */
-
        mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
        /* Select the region size and the sub-region map */
-
        l2size = mpu_log2regionceil(size);
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-
        /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) except cortex-r4(S(0)) */
-
-       regval =                                        /* Not Cacheable  */
-               MPU_RACR_B |                    /* Not Bufferable */
+       regval =                                          /* Not Cacheable  */
+                MPU_RACR_B                             | /* Not Bufferable */
 #if !defined(CONFIG_ARCH_CORTEXR4)
-               MPU_RACR_S |                    /* Shareable      */
+                MPU_RACR_S                             | /* Shareable      */
 #endif
-               MPU_RACR_TEX(5) |               /* TEX */
-               MPU_RACR_AP_RWRW;               /* P:RW   U:RW */
+                MPU_RACR_TEX(5)                        | /* TEX            */
+                MPU_RACR_AP_RWRW;                        /* P:RW   U:RW    */
        mpu_set_dracr(regval);
 
-       regval = MPU_RASR_ENABLE |      /* Enable region */
-                        MPU_RASR_RSIZE_LOG2((uint32_t)l2size) |        /* Region size   */
-                        ((uint32_t)subregions << MPU_RASR_SRD_SHIFT);  /* Sub-regions   */
+       regval = MPU_RASR_ENABLE                        | /* Enable region */
+                MPU_RASR_RSIZE_LOG2((uint32_t)l2size)  | /* Region size   */
+                ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
        mpu_set_drsr(regval);
 }
 
@@ -1035,5 +996,5 @@ static inline void mpu_user_intsram_wb(uintptr_t base, size_t size, int region)
 }
 #endif
 
-#endif                                                 /* __ASSEMBLY__ */
-#endif                                                 /* __ARCH_ARM_SRC_ARMV7R_MPU_H */
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_ARMV7R_MPU_H */