Record right reg num of thumb special data instructions

When GDB decodes these thumb special data instructions, such as 'mov sp, r7'
the Rd is got incorrectly.  According to the arch reference manual, the Rd
is DN:Rdn, in which DN is bit 7 and Rdn is bits 0 to 2.  This patch fixes it.

gdb:

2016-02-26  Yao Qi  <yao.qi@linaro.org>

	* arm-tdep.c (thumb_record_ld_st_reg_offset): Fix the register
	number of Rd.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index fe3aa36..36cbef6 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2016-02-26  Yao Qi  <yao.qi@linaro.org>
+
+       * arm-tdep.c (thumb_record_ld_st_reg_offset): Fix the register
+       number of Rd.
+
 2016-02-25  Doug Evans  <dje@google.com>
 
        * remote-m32r-sdi.c (recv_char_data): Initialize val to avoid

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 17f6fc6..bd0ee97 100644 (file)
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -11512,10 +11512,10 @@ thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
         }
       else
         {
-          /* Format 8; special data processing insns.  */
-          reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
-          record_buf[0] = ARM_PS_REGNUM;
-          record_buf[1] = reg_src1;
+         /* Format 8; special data processing insns.  */
+         record_buf[0] = ARM_PS_REGNUM;
+         record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3
+                          | bits (thumb_insn_r->arm_insn, 0, 2));
           thumb_insn_r->reg_rec_count = 2;
         }
     }