[AArch64][SVE] Implement isVScaleKnownToBeAPowerOfTwo

According to https://developer.arm.com/documentation/102105/ia-00/?lang=en

> Arm is making a retrospective change to the SVE architecture to remove
> the capability of selecting a non-power-of-two vector length in
> non-Streaming SVE as well as in Streaming SVE mode. Specific updates as
> a result of this change will be communicated in due course.

This patch implements the isVScaleKnownToBeAPowerOfTwo method to teach
DAG Combines that VScale will be known to be a power of 2, which helps
reduce or simplify some expressions (notably the udiv in vector trip
count expressions).

Differential Revision: https://reviews.llvm.org/D141486

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 511c103..7834277 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6083,6 +6083,10 @@ bool AArch64TargetLowering::mergeStoresAfterLegalization(EVT VT) const {
   return !Subtarget->useSVEForFixedLengthVectors();
 }
 
+bool AArch64TargetLowering::isVScaleKnownToBeAPowerOfTwo() const {
+  return true;
+}
+
 bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
     EVT VT, bool OverrideNEON) const {
   if (!VT.isFixedLengthVector() || !VT.isSimple())

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index febb116..3731c5a 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -907,6 +907,8 @@ public:
                               SDValue Chain, SDValue InFlag,
                               SDValue PStateSM, bool Entry) const;
 
+  bool isVScaleKnownToBeAPowerOfTwo() const override;
+
   // Normally SVE is only used for byte size vectors that do not fit within a
   // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
   // used for 64bit and 128bit vectors as well.

diff --git a/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll b/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
index 0d58f98..2012923 100644 (file)
--- a/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
+++ b/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
@@ -7,8 +7,8 @@ define i64 @vscale_lshr(i64 %TC) {
 ; CHECK-NEXT:    rdvl x8, #1
 ; CHECK-NEXT:    lsr x8, x8, #4
 ; CHECK-NEXT:    lsr x8, x8, #3
-; CHECK-NEXT:    udiv x9, x0, x8
-; CHECK-NEXT:    msub x0, x9, x8, x0
+; CHECK-NEXT:    sub x8, x8, #1
+; CHECK-NEXT:    and x0, x0, x8
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %shifted = lshr i64 %vscale, 3
@@ -21,8 +21,8 @@ define i64 @vscale(i64 %TC) {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    rdvl x8, #1
 ; CHECK-NEXT:    lsr x8, x8, #4
-; CHECK-NEXT:    udiv x9, x0, x8
-; CHECK-NEXT:    msub x0, x9, x8, x0
+; CHECK-NEXT:    sub x8, x8, #1
+; CHECK-NEXT:    and x0, x0, x8
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %urem = urem i64 %TC, %vscale
@@ -33,8 +33,8 @@ define i64 @vscale_shl(i64 %TC) {
 ; CHECK-LABEL: vscale_shl:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cnth x8
-; CHECK-NEXT:    udiv x9, x0, x8
-; CHECK-NEXT:    msub x0, x9, x8, x0
+; CHECK-NEXT:    sub x8, x8, #1
+; CHECK-NEXT:    and x0, x0, x8
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %shifted = shl i64 %vscale, 3