A64: Let the Simulator trap BLR XZR instructions.
authoralexandre.rames@arm.com <alexandre.rames@arm.com@ce2b1a6d-e550-0410-aec6-3dcde31c8c00>
Tue, 18 Feb 2014 17:10:04 +0000 (17:10 +0000)
committeralexandre.rames@arm.com <alexandre.rames@arm.com@ce2b1a6d-e550-0410-aec6-3dcde31c8c00>
Tue, 18 Feb 2014 17:10:04 +0000 (17:10 +0000)
This instruction is used as a guard for the constant pool.

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/170673003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19461 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

src/a64/simulator-a64.cc

index e0a0d62..014b714 100644 (file)
@@ -986,6 +986,11 @@ void Simulator::VisitUnconditionalBranchToRegister(Instruction* instr) {
   switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
     case BLR: {
       set_lr(instr->NextInstruction());
+      if (instr->Rn() == 31) {
+        // BLR XZR is used as a guard for the constant pool. We should never hit
+        // this, but if we do trap to allow debugging.
+        Debug();
+      }
       // Fall through.
     }
     case BR: