XPedite5200 board support cleanup
authorPeter Tyser <ptyser@xes-inc.com>
Tue, 23 Dec 2008 22:32:00 +0000 (16:32 -0600)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Mon, 29 Dec 2008 18:46:36 +0000 (12:46 -0600)
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
board/xes/common/actl_nand.c [new file with mode: 0644]
board/xes/common/fsl_85xx_pci.c
board/xes/xpedite5200/Makefile [new file with mode: 0644]
board/xes/xpedite5200/config.mk [new file with mode: 0644]
board/xes/xpedite5200/ddr.c [new file with mode: 0644]
board/xes/xpedite5200/law.c [new file with mode: 0644]
board/xes/xpedite5200/tlb.c [new file with mode: 0644]
board/xes/xpedite5200/u-boot.lds [new file with mode: 0644]
board/xes/xpedite5200/xpedite5200.c [new file with mode: 0644]
include/configs/XPEDITE5200.h [new file with mode: 0644]

diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c
new file mode 100644 (file)
index 0000000..465aeb0
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+       struct nand_chip *this = mtd->priv;
+       ulong IO_ADDR_W;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+               IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+                               CONFIG_SYS_NAND_ACTL_ALE |
+                               CONFIG_SYS_NAND_ACTL_NCE);
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+               if (ctrl & NAND_NCE)
+                       IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+               this->IO_ADDR_W = (void *)IO_ADDR_W;
+       }
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+       nand->ecc.mode = NAND_ECC_SOFT;
+       nand->cmd_ctrl = nand_addr_hwcontrol;
+       nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+       return 0;
+}
index 56f3447..cd65a73 100644 (file)
@@ -179,7 +179,7 @@ void pci_init_board(void)
 
                fsl_pci_init(hose);
 
-               first_free_busno = hose->last_busno+1;
+               first_free_busno = hose->last_busno + 1;
                printf("    PCI1 on bus %02x - %02x\n",
                        hose->first_busno, hose->last_busno);
        } else {
@@ -289,7 +289,7 @@ void pci_init_board(void)
                if (!host)
                        fsl_pci_config_unlock(hose);
 
-               first_free_busno = hose->last_busno+1;
+               first_free_busno = hose->last_busno + 1;
                printf("    PCIE2 on bus %02x - %02x\n",
                                hose->first_busno, hose->last_busno);
        }
@@ -343,7 +343,7 @@ void pci_init_board(void)
                if (!host)
                        fsl_pci_config_unlock(hose);
 
-               first_free_busno = hose->last_busno+1;
+               first_free_busno = hose->last_busno + 1;
                printf("    PCIE3 on bus %02x - %02x\n",
                                hose->first_busno, hose->last_busno);
        }
diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite5200/Makefile
new file mode 100644 (file)
index 0000000..02fe8fc
--- /dev/null
@@ -0,0 +1,55 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y        += $(BOARD).o
+COBJS-y        += ddr.o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+
+SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(OBJS) $(SOBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xes/xpedite5200/config.mk b/board/xes/xpedite5200/config.mk
new file mode 100644 (file)
index 0000000..be5a5c3
--- /dev/null
@@ -0,0 +1,34 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# xpedite5200 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
+PLATFORM_CPPFLAGS += -mrelocatable
diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite5200/ddr.c
new file mode 100644 (file)
index 0000000..c5616d5
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+       i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+       /* We use soldered memory, but use an SPD EEPROM to describe it.
+        * The SPD has an unspecified dimm type, but the DDR2 initialization
+        * code requires a specific type to be specified. This sets the type
+        * as a standard unregistered SO-DIMM. */
+       if (spd->dimm_type == 0) {
+               spd->dimm_type = 0x4;
+               ((uchar *)spd)[63] += 0x4;
+       }
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+       return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+                       unsigned int ctrl_num)
+{
+       unsigned int i;
+
+       if (ctrl_num) {
+               printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
+               return;
+       }
+
+       for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
+               get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       /*
+        * Factors to consider for clock adjust:
+        *      - number of chips on bus
+        *      - position of slot
+        *      - DDR1 vs. DDR2?
+        *      - ???
+        *
+        * This needs to be determined on a board-by-board basis.
+        *      0110    3/4 cycle late
+        *      0111    7/8 cycle late
+        */
+       popts->clk_adjust = 7;
+
+       /*
+        * Factors to consider for CPO:
+        *      - frequency
+        *      - ddr1 vs. ddr2
+        */
+       popts->cpo_override = 9;
+
+       /*
+        * Factors to consider for write data delay:
+        *      - number of DIMMs
+        *
+        * 1 = 1/4 clock delay
+        * 2 = 1/2 clock delay
+        * 3 = 3/4 clock delay
+        * 4 = 1   clock delay
+        * 5 = 5/4 clock delay
+        * 6 = 3/2 clock delay
+        */
+       popts->write_data_delay = 3;
+
+       /*
+        * Factors to consider for half-strength driver enable:
+        *      - number of DIMMs installed
+        */
+       popts->half_strength_driver_enable = 0;
+}
diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c
new file mode 100644 (file)
index 0000000..386f9c5
--- /dev/null
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+       /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+       SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#if CONFIG_SYS_PCI1_MEM_PHYS
+       SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
+       SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
+#endif
+#if CONFIG_SYS_PCI2_MEM_PHYS
+       SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
+       SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite5200/tlb.c
new file mode 100644 (file)
index 0000000..bd7bff8
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+               MAS3_SX|MAS3_SW|MAS3_SR, 0,
+               0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+               CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+               MAS3_SX|MAS3_SW|MAS3_SR, 0,
+               0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+               CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+               MAS3_SX|MAS3_SW|MAS3_SR, 0,
+               0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+               CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+               MAS3_SX|MAS3_SW|MAS3_SR, 0,
+               0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* W**G* - NOR flashes */
+       /* This will be changed to *I*G* after relocation to RAM. */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+               0, 0, BOOKE_PAGESZ_256M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, 1, BOOKE_PAGESZ_1M, 1),
+
+       /* *I*G* - NAND flash */
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+       /* *I*G* - PCI MEM */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+       /* *I*G* - PCI MEM */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+       /* *I*G* - PCI IO */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite5200/u-boot.lds b/board/xes/xpedite5200/u-boot.lds
new file mode 100644 (file)
index 0000000..bd952d2
--- /dev/null
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) + 0x7f000 :
+  {
+    cpu/mpc85xx/start.o        (.bootpg)
+  } :text = 0xffff
+
+  .resetvec ADDR(.text) + 0x7fffc :
+  {
+    *(.resetvec)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x80000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c
new file mode 100644 (file)
index 0000000..e266d1d
--- /dev/null
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+int checkboard(void)
+{
+       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+       char *s;
+
+       printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
+       printf("       ");
+       s = getenv("board_rev");
+       if (s)
+               printf("Rev %s, ", s);
+       s = getenv("serial#");
+       if (s)
+               printf("Serial# %s, ", s);
+       s = getenv("board_cfg");
+       if (s)
+               printf("Cfg %s", s);
+       printf("\n");
+
+       lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
+       lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
+       ecm->eedr = 0xffffffff;         /* Clear ecm errors */
+       ecm->eeer = 0xffffffff;         /* Enable ecm errors */
+
+       return 0;
+}
+
+static void flash_cs_fixup(void)
+{
+       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       int flash_sel;
+
+       /*
+        * Print boot dev and swap flash flash chip selects if booted from 2nd
+        * flash.  Swapping chip selects presents user with a common memory
+        * map regardless of which flash was booted from.
+        */
+       flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+                       CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+       printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+       if (flash_sel) {
+               lbc->br0 = CONFIG_SYS_BR1_PRELIM;
+               lbc->or0 = CONFIG_SYS_OR1_PRELIM;
+
+               lbc->br1 = CONFIG_SYS_BR0_PRELIM;
+               lbc->or1 = CONFIG_SYS_OR0_PRELIM;
+       }
+}
+
+int board_early_init_r(void)
+{
+       /* Initialize PCA9557 devices */
+       pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+       pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+       /*
+        * Remap NOR flash region to caching-inhibited
+        * so that flash can be erased/programmed properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       /* Invalidate existing TLB entry for NOR flash */
+       disable_tlb(0);
+       set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+               (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, 0, BOOKE_PAGESZ_256M, 1);
+
+       flash_cs_fixup();
+
+       return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+       ft_board_pci_setup(blob, bd);
+#endif
+       ft_cpu_setup(blob, bd);
+}
+#endif
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
new file mode 100644 (file)
index 0000000..1df6855
--- /dev/null
@@ -0,0 +1,546 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5200 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE           1       /* BOOKE */
+#define CONFIG_E500            1       /* BOOKE e500 family */
+#define CONFIG_MPC85xx         1       /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548         1
+#define CONFIG_XPEDITE5200     1
+#define CONFIG_SYS_BOARD_NAME  "XPedite5200"
+#define CONFIG_BOARD_EARLY_INIT_R      /* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS       /* Fully relocate to SDRAM */
+
+#define CONFIG_PCI             1       /* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP         1       /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW   1       /* show pci devices on startup */
+#define CONFIG_PCI1            1       /* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW         1       /* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
+#define SPD_EEPROM_ADDRESS             0x54
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ    66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                        /* toggle L2 cache */
+#define CONFIG_BTB                     /* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS       1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR             0xef000000      /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS        CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCI1_ADDR   (CONFIG_SYS_CCSRBAR + 0x8000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff     DDR                     2G Cacheable
+ * 0x8000_0000 0xbfff_ffff     PCI1 Mem                1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff     PCI1 IO                 8M non-cacheable
+ * 0xef00_0000 0xef0f_ffff     CCSR/IMMR               1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff     NAND Flash              1M non-cacheable
+ * 0xf800_0000 0xfbff_ffff     NOR Flash 2             64M non-cacheable
+ * 0xfc00_0000 0xffff_ffff     NOR Flash 1             64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR    (LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE           0xef800000
+#define CONFIG_SYS_NAND_BASE2          0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE       (1 << 3)        /* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE       (1 << 4)        /* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE       (0)             /* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY     25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE          0xfc000000
+#define CONFIG_SYS_FLASH_BASE2         0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS     2               /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      1024            /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST      { {0xfff40000, 0xc0000}, \
+                                                 {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE       /* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE  | \
+                                BR_PS_16               | \
+                                BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_64MB             | \
+                                OR_GPCM_ACS_DIV4       | \
+                                OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_FLASH_BASE2 | \
+                                BR_PS_16               | \
+                                BR_V)
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_NAND_BASE   | \
+                                BR_PS_8                | \
+                                BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256KB            | \
+                                OR_GPCM_BCTLD          | \
+                                OR_GPCM_CSNT           | \
+                                OR_GPCM_ACS_DIV4       | \
+                                OR_GPCM_SCY_4          | \
+                                OR_GPCM_TRLX           | \
+                                OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_NAND_BASE2  | \
+                                BR_PS_8                | \
+                                BR_V)
+#define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK       1
+#define CONFIG_SYS_INIT_RAM_ADDR       0xe0000000
+#define CONFIG_SYS_INIT_RAM_END                0x4000
+
+#define CONFIG_SYS_GBL_DATA_SIZE       128             /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)    /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)   /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_LOADS_ECHO              1       /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT               1
+#define CONFIG_OF_BOARD_SETUP          1
+#define CONFIG_OF_STDOUT_VIA_ALIAS     1
+
+#define CONFIG_SYS_64BIT_VSPRINTF      1
+#define CONFIG_SYS_64BIT_STRTOUL       1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C                         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                                /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_OFFSET          0x3000
+#define CONFIG_SYS_I2C2_OFFSET         0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR             0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      6       /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10      /* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11                      1
+#define CONFIG_SYS_I2C_RTC_ADDR                        0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR            2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0           0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1           0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR            CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0            0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1            0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2            0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0           0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS       0x10
+#define CONFIG_SYS_PCA953X_FLASH_WP            0x20
+#define CONFIG_SYS_PCA953X_MONARCH             0x40
+#define CONFIG_SYS_PCA953X_EREADY              0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0             0x01
+#define CONFIG_SYS_PCA953X_P14_IO1             0x02
+#define CONFIG_SYS_PCA953X_P14_IO2             0x04
+#define CONFIG_SYS_PCA953X_P14_IO3             0x08
+#define CONFIG_SYS_PCA953X_P14_IO4             0x10
+#define CONFIG_SYS_PCA953X_P14_IO5             0x20
+#define CONFIG_SYS_PCA953X_P14_IO6             0x40
+#define CONFIG_SYS_PCA953X_P14_IO7             0x80
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE       0x40000000      /* 1G */
+#define CONFIG_SYS_PCI1_IO_BASE                0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS                0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE                0x00800000      /* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET               /* tsec ethernet support */
+#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI       1
+#define CONFIG_MII             1       /* MII PHY management */
+#define CONFIG_ETHPRIME                "eTSEC1"
+
+#define CONFIG_TSEC1           1
+#define CONFIG_TSEC1_NAME      "eTSEC1"
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC1_PHY_ADDR         1
+#define TSEC1_PHYIDX           0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2           1
+#define CONFIG_TSEC2_NAME      "eTSEC2"
+#define TSEC2_FLAGS            TSEC_GIGABIT
+#define TSEC2_PHY_ADDR         2
+#define TSEC2_PHYIDX           0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3   1
+#define CONFIG_TSEC3_NAME      "eTSEC3"
+#define TSEC3_FLAGS            TSEC_GIGABIT
+#define TSEC3_PHY_ADDR         3
+#define TSEC3_PHYIDX           0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4   1
+#define CONFIG_TSEC4_NAME      "eTSEC4"
+#define TSEC4_FLAGS            TSEC_GIGABIT
+#define TSEC4_PHY_ADDR         4
+#define TSEC4_PHYIDX           0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ          1000            /* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING 1               /* add command line history     */
+#define CONFIG_LOADADDR                0x1000000       /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY       3               /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG                      /* do not reset board on panic */
+#define CONFIG_PREBOOT                         /* enable preboot variable */
+#define CONFIG_FIT             1
+#define CONFIG_FIT_VERBOSE     1
+#define CONFIG_INTEGRITY                       /* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS              /* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ   (16 << 20)      /* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD          0x01            /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM          0x02            /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE   0x20000         /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE                0x8000
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff     Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff     Sec FDT (256KB)
+ * faf00000 - fbefffff     Sec OS image (16MB)
+ * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR   MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR   MK_STR(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR    MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR    MK_STR(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1                                             \
+       "$download_cmd $loadaddr $ubootfile; "                          \
+       "if test $? -eq 0; then "                                       \
+               "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
+               "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
+               "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
+               "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
+               "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
+               "if test $? -ne 0; then "                               \
+                       "echo PROGRAM FAILED; "                         \
+               "else; "                                                \
+                       "echo PROGRAM SUCCEEDED; "                      \
+               "fi; "                                                  \
+       "else; "                                                        \
+               "echo DOWNLOAD FAILED; "                                \
+       "fi;"
+
+#define CONFIG_PROG_UBOOT2                                             \
+       "$download_cmd $loadaddr $ubootfile; "                          \
+       "if test $? -eq 0; then "                                       \
+               "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
+               "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
+               "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
+               "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
+               "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
+               "if test $? -ne 0; then "                               \
+                       "echo PROGRAM FAILED; "                         \
+               "else; "                                                \
+                       "echo PROGRAM SUCCEEDED; "                      \
+               "fi; "                                                  \
+       "else; "                                                        \
+               "echo DOWNLOAD FAILED; "                                \
+       "fi;"
+
+#define CONFIG_BOOT_OS_NET                                             \
+       "$download_cmd $osaddr $osfile; "                               \
+       "if test $? -eq 0; then "                                       \
+               "if test -n $fdtaddr; then "                            \
+                       "$download_cmd $fdtaddr $fdtfile; "             \
+                       "if test $? -eq 0; then "                       \
+                               "bootm $osaddr - $fdtaddr; "            \
+                       "else; "                                        \
+                               "echo FDT DOWNLOAD FAILED; "            \
+                       "fi; "                                          \
+               "else; "                                                \
+                       "bootm $osaddr; "                               \
+               "fi; "                                                  \
+       "else; "                                                        \
+               "echo OS DOWNLOAD FAILED; "                             \
+       "fi;"
+
+#define CONFIG_PROG_OS1                                                        \
+       "$download_cmd $osaddr $osfile; "                               \
+       "if test $? -eq 0; then "                                       \
+               "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
+               "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
+               "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
+               "if test $? -ne 0; then "                               \
+                       "echo OS PROGRAM FAILED; "                      \
+               "else; "                                                \
+                       "echo OS PROGRAM SUCCEEDED; "                   \
+               "fi; "                                                  \
+       "else; "                                                        \
+               "echo OS DOWNLOAD FAILED; "                             \
+       "fi;"
+
+#define CONFIG_PROG_OS2                                                        \
+       "$download_cmd $osaddr $osfile; "                               \
+       "if test $? -eq 0; then "                                       \
+               "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
+               "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
+               "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
+               "if test $? -ne 0; then "                               \
+                       "echo OS PROGRAM FAILED; "                      \
+               "else; "                                                \
+                       "echo OS PROGRAM SUCCEEDED; "                   \
+               "fi; "                                                  \
+       "else; "                                                        \
+               "echo OS DOWNLOAD FAILED; "                             \
+       "fi;"
+
+#define CONFIG_PROG_FDT1                                               \
+       "$download_cmd $fdtaddr $fdtfile; "                             \
+       "if test $? -eq 0; then "                                       \
+               "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
+               "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
+               "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
+               "if test $? -ne 0; then "                               \
+                       "echo FDT PROGRAM FAILED; "                     \
+               "else; "                                                \
+                       "echo FDT PROGRAM SUCCEEDED; "                  \
+               "fi; "                                                  \
+       "else; "                                                        \
+               "echo FDT DOWNLOAD FAILED; "                            \
+       "fi;"
+
+#define CONFIG_PROG_FDT2                                               \
+       "$download_cmd $fdtaddr $fdtfile; "                             \
+       "if test $? -eq 0; then "                                       \
+               "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
+               "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
+               "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
+               "if test $? -ne 0; then "                               \
+                       "echo FDT PROGRAM FAILED; "                     \
+               "else; "                                                \
+                       "echo FDT PROGRAM SUCCEEDED; "                  \
+               "fi; "                                                  \
+       "else; "                                                        \
+               "echo FDT DOWNLOAD FAILED; "                            \
+       "fi;"
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "autoload=yes\0"                                                \
+       "download_cmd=tftp\0"                                           \
+       "console_args=console=ttyS0,115200\0"                           \
+       "root_args=root=/dev/nfs rw\0"                                  \
+       "misc_args=ip=on\0"                                             \
+       "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+       "bootfile=/home/user/file\0"                                    \
+       "osfile=/home/user/uImage-XPedite5200\0"                        \
+       "fdtfile=/home/user/xpedite5200.dtb\0"                          \
+       "ubootfile=/home/user/u-boot.bin\0"                             \
+       "fdtaddr=c00000\0"                                              \
+       "osaddr=0x1000000\0"                                            \
+       "loadaddr=0x1000000\0"                                          \
+       "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
+       "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
+       "prog_os1="CONFIG_PROG_OS1"\0"                                  \
+       "prog_os2="CONFIG_PROG_OS2"\0"                                  \
+       "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
+       "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
+       "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
+       "bootcmd_flash1=run set_bootargs; "                             \
+               "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+       "bootcmd_flash2=run set_bootargs; "                             \
+               "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+       "bootcmd=run bootcmd_flash1\0"
+#endif /* __CONFIG_H */