#define MGA_MISC_OUT 0x1fc2
#define MGA_MISC_IN 0x1fcc
+/*
+ * TODO: This is a pretty large set of default values for all kinds of
+ * settings. It should be split and set in the various DRM helpers,
+ * such as the CRTC reset or atomic_enable helpers. The PLL values
+ * probably belong to each model's PLL code.
+ */
+#define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp) \
+ /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, \
+ /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 0x18: */ (xvrefctrl), \
+ /* 0x19: */ 0, \
+ /* 0x1a: */ (xpixclkctrl), \
+ /* 0x1b: */ 0xff, 0xbf, 0x20, \
+ /* 0x1e: */ (xmiscctrl), \
+ /* 0x1f: */ 0x20, \
+ /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+ /* 0x28: */ 0x00, 0x00, 0x00, 0x00, \
+ /* 0x2c: */ (xsyspllm), \
+ /* 0x2d: */ (xsysplln), \
+ /* 0x2e: */ (xsyspllp), \
+ /* 0x2f: */ 0x40, \
+ /* 0x30: */ 0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83, \
+ /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a, \
+ /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 \
+
#define MGAG200_MAX_FB_HEIGHT 4096
#define MGAG200_MAX_FB_WIDTH 4096
enum mga_type type);
struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
enum mga_type type);
+void mgag200_g200wb_init_registers(struct mga_device *mdev);
struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
enum mga_type type);
struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
enum mga_type type);
+void mgag200_g200eh_init_registers(struct mga_device *mdev);
struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
enum mga_type type);
struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
/* mgag200_mode.c */
resource_size_t mgag200_device_probe_vram(struct mga_device *mdev);
+void mgag200_init_registers(struct mga_device *mdev);
int mgag200_modeset_init(struct mga_device *mdev, resource_size_t vram_fb_available);
/* mgag200_i2c.c */
return mgag200_init_pci_options(pdev, option, 0x00008000);
}
+static void mgag200_g200_init_registers(struct mgag200_g200_device *g200)
+{
+ static const u8 dacvalue[] = {
+ MGAG200_DAC_DEFAULT(0x00, 0xc9, 0x1f,
+ 0x04, 0x2d, 0x19)
+ };
+
+ struct mga_device *mdev = &g200->base;
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(dacvalue); ++i) {
+ if ((i <= 0x17) ||
+ (i == 0x1b) ||
+ (i == 0x1c) ||
+ ((i >= 0x1f) && (i <= 0x29)) ||
+ ((i >= 0x30) && (i <= 0x37)))
+ continue;
+ WREG_DAC(i, dacvalue[i]);
+ }
+
+ mgag200_init_registers(mdev);
+}
+
/*
* DRM Device
*/
if (ret)
return ERR_PTR(ret);
+ mgag200_g200_init_registers(g200);
+
vram_available = mgag200_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
#include "mgag200_drv.h"
+void mgag200_g200eh_init_registers(struct mga_device *mdev)
+{
+ static const u8 dacvalue[] = {
+ MGAG200_DAC_DEFAULT(0x00, 0xc9,
+ MGA1064_MISC_CTL_VGA8 | MGA1064_MISC_CTL_DAC_RAM_CS,
+ 0x00, 0x00, 0x00)
+ };
+
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
+ if ((i <= 0x17) ||
+ (i == 0x1b) ||
+ (i == 0x1c) ||
+ ((i >= 0x1f) && (i <= 0x29)) ||
+ ((i >= 0x30) && (i <= 0x37)) ||
+ ((i >= 0x44) && (i <= 0x4e)))
+ continue;
+ WREG_DAC(i, dacvalue[i]);
+ }
+
+ mgag200_init_registers(mdev);
+}
+
/*
* DRM device
*/
if (ret)
return ERR_PTR(ret);
+ mgag200_g200eh_init_registers(mdev);
+
vram_available = mgag200_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
if (ret)
return ERR_PTR(ret);
+ mgag200_g200eh_init_registers(mdev); // same as G200EH
+
vram_available = mgag200_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
#include "mgag200_drv.h"
+static void mgag200_g200er_init_registers(struct mga_device *mdev)
+{
+ static const u8 dacvalue[] = {
+ MGAG200_DAC_DEFAULT(0x00, 0xc9, 0x1f, 0x00, 0x00, 0x00)
+ };
+
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
+ if ((i <= 0x17) ||
+ (i == 0x1b) ||
+ (i == 0x1c) ||
+ ((i >= 0x1f) && (i <= 0x29)) ||
+ ((i >= 0x30) && (i <= 0x37)))
+ continue;
+ WREG_DAC(i, dacvalue[i]);
+ }
+
+ WREG_DAC(0x90, 0); /* G200ER specific */
+
+ mgag200_init_registers(mdev);
+}
+
/*
* DRM device
*/
if (ret)
return ERR_PTR(ret);
+ mgag200_g200er_init_registers(mdev);
+
vram_available = mgag200_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
#include "mgag200_drv.h"
+static void mgag200_g200ev_init_registers(struct mga_device *mdev)
+{
+ static const u8 dacvalue[] = {
+ MGAG200_DAC_DEFAULT(0x00,
+ MGA1064_PIX_CLK_CTL_SEL_PLL,
+ MGA1064_MISC_CTL_VGA8 | MGA1064_MISC_CTL_DAC_RAM_CS,
+ 0x00, 0x00, 0x00)
+ };
+
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
+ if ((i <= 0x17) ||
+ (i == 0x1b) ||
+ (i == 0x1c) ||
+ ((i >= 0x1f) && (i <= 0x29)) ||
+ ((i >= 0x30) && (i <= 0x37)) ||
+ ((i >= 0x44) && (i <= 0x4e)))
+ continue;
+ WREG_DAC(i, dacvalue[i]);
+ }
+
+ mgag200_init_registers(mdev);
+}
+
/*
* DRM device
*/
if (ret)
return ERR_PTR(ret);
+ mgag200_g200ev_init_registers(mdev);
+
vram_available = mgag200_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
if (ret)
return ERR_PTR(ret);
+ mgag200_g200wb_init_registers(mdev); // same as G200WB
+
vram_available = mgag200_g200ew3_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
return mgag200_init_pci_options(pdev, option, 0x00008000);
}
+static void mgag200_g200se_init_registers(struct mgag200_g200se_device *g200se)
+{
+ static const u8 dacvalue[] = {
+ MGAG200_DAC_DEFAULT(0x03,
+ MGA1064_PIX_CLK_CTL_SEL_PLL,
+ MGA1064_MISC_CTL_DAC_EN |
+ MGA1064_MISC_CTL_VGA8 |
+ MGA1064_MISC_CTL_DAC_RAM_CS,
+ 0x00, 0x00, 0x00)
+ };
+
+ struct mga_device *mdev = &g200se->base;
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
+ if ((i <= 0x17) ||
+ (i == 0x1b) ||
+ (i == 0x1c) ||
+ ((i >= 0x1f) && (i <= 0x29)) ||
+ ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)) ||
+ ((i >= 0x30) && (i <= 0x37)))
+ continue;
+ WREG_DAC(i, dacvalue[i]);
+ }
+
+ mgag200_init_registers(mdev);
+}
+
/*
* DRM device
*/
if (ret)
return ERR_PTR(ret);
+ mgag200_g200se_init_registers(g200se);
+
vram_available = mgag200_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
#include "mgag200_drv.h"
+void mgag200_g200wb_init_registers(struct mga_device *mdev)
+{
+ static const u8 dacvalue[] = {
+ MGAG200_DAC_DEFAULT(0x07, 0xc9, 0x1f, 0x00, 0x00, 0x00)
+ };
+
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
+ if ((i <= 0x17) ||
+ (i == 0x1b) ||
+ (i == 0x1c) ||
+ ((i >= 0x1f) && (i <= 0x29)) ||
+ ((i >= 0x30) && (i <= 0x37)) ||
+ ((i >= 0x44) && (i <= 0x4e)))
+ continue;
+ WREG_DAC(i, dacvalue[i]);
+ }
+
+ mgag200_init_registers(mdev);
+}
+
/*
* DRM device
*/
if (ret)
return ERR_PTR(ret);
+ mgag200_g200wb_init_registers(mdev);
+
vram_available = mgag200_device_probe_vram(mdev);
ret = mgag200_modeset_init(mdev, vram_available);
WREG_ECRT(0x00, crtcext0);
}
-static void mgag200_set_dac_regs(struct mga_device *mdev)
-{
- size_t i;
- u8 dacvalue[] = {
- /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
- /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
- /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
- /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
- /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
- /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
- /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
- /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
- /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
- };
-
- switch (mdev->type) {
- case G200_PCI:
- case G200_AGP:
- dacvalue[MGA1064_SYS_PLL_M] = 0x04;
- dacvalue[MGA1064_SYS_PLL_N] = 0x2D;
- dacvalue[MGA1064_SYS_PLL_P] = 0x19;
- break;
- case G200_SE_A:
- case G200_SE_B:
- dacvalue[MGA1064_VREF_CTL] = 0x03;
- dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
- dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
- MGA1064_MISC_CTL_VGA8 |
- MGA1064_MISC_CTL_DAC_RAM_CS;
- break;
- case G200_WB:
- case G200_EW3:
- dacvalue[MGA1064_VREF_CTL] = 0x07;
- break;
- case G200_EV:
- dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
- dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
- MGA1064_MISC_CTL_DAC_RAM_CS;
- break;
- case G200_EH:
- case G200_EH3:
- dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
- MGA1064_MISC_CTL_DAC_RAM_CS;
- break;
- case G200_ER:
- break;
- }
-
- for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
- if ((i <= 0x17) ||
- (i == 0x1b) ||
- (i == 0x1c) ||
- ((i >= 0x1f) && (i <= 0x29)) ||
- ((i >= 0x30) && (i <= 0x37)))
- continue;
- if (IS_G200_SE(mdev) &&
- ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
- continue;
- if ((mdev->type == G200_EV ||
- mdev->type == G200_WB ||
- mdev->type == G200_EH ||
- mdev->type == G200_EW3 ||
- mdev->type == G200_EH3) &&
- (i >= 0x44) && (i <= 0x4e))
- continue;
-
- WREG_DAC(i, dacvalue[i]);
- }
-
- if (mdev->type == G200_ER)
- WREG_DAC(0x90, 0);
-}
-
-static void mgag200_init_regs(struct mga_device *mdev)
+void mgag200_init_registers(struct mga_device *mdev)
{
u8 crtc11, misc;
- mgag200_set_dac_regs(mdev);
-
WREG_SEQ(2, 0x0f);
WREG_SEQ(3, 0x00);
WREG_SEQ(4, 0x0e);
struct drm_device *dev = &mdev->base;
int ret;
- mgag200_init_regs(mdev);
-
ret = mgag200_mode_config_init(mdev, vram_available);
if (ret)
return ret;