[DAG] matchRotateSub - set demanded bits to the shift amount type size, not the shift...

This should fix a report on D130251 of an assert due to a bitwidth mismatch in APInt::isSubSetOf

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 21bad73..6548791 100644 (file)
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7301,7 +7301,8 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
   unsigned MaskLoBits = 0;
   if (IsRotate && isPowerOf2_64(EltSize)) {
     unsigned Bits = Log2_64(EltSize);
-    APInt DemandedBits = APInt::getLowBitsSet(EltSize, Bits);
+    APInt DemandedBits =
+        APInt::getLowBitsSet(Neg.getScalarValueSizeInBits(), Bits);
     if (SDValue Inner =
             TLI.SimplifyMultipleUseDemandedBits(Neg, DemandedBits, DAG)) {
       Neg = Inner;
@@ -7321,7 +7322,8 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
   // affect Mask's demanded bits, just replace Pos with Pos'. These operations
   // are redundant for the purpose of the equality.
   if (MaskLoBits) {
-    APInt DemandedBits = APInt::getLowBitsSet(EltSize, MaskLoBits);
+    APInt DemandedBits =
+        APInt::getLowBitsSet(Pos.getScalarValueSizeInBits(), MaskLoBits);
     if (SDValue Inner =
             TLI.SimplifyMultipleUseDemandedBits(Pos, DemandedBits, DAG)) {
       Pos = Inner;