Merge tag 'fsl-qoriq-2022-8-17' of https://source.denx.de/u-boot/custodians/u-boot...

Enable SPL authentication for ls1021atwr
Fdt fixups for ls1043ardb v7.0 board

diff --git a/MAINTAINERS b/MAINTAINERS
index fa8c13f..5857fbf 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1499,5 +1499,6 @@ F:        */
 CAAM
 M:     Gaurav Jain <gaurav.jain@nxp.com>
 S:     Maintained
+F:     arch/arm/dts/ls1021a-twr-u-boot.dtsi
 F:     drivers/crypto/fsl/
 F:     include/fsl_sec.h

diff --git a/arch/arm/dts/ls1021a-twr-u-boot.dtsi b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
new file mode 100644 (file)
index 0000000..3711e42
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 NXP
+ */
+
+&{/soc} {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+};
+
+&crypto {
+       u-boot,dm-spl;
+};
+
+&sec_jr0 {
+       u-boot,dm-spl;
+};
+
+&sec_jr1 {
+       u-boot,dm-spl;
+};
+
+&sec_jr2 {
+       u-boot,dm-spl;
+};
+
+&sec_jr3 {
+       u-boot,dm-spl;
+};

diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index bf96af7..82df2f1 100644 (file)
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include "ls1021a.dtsi"
+#include "ls1021a-twr-u-boot.dtsi"
 
 / {
        model = "LS1021A TWR Board";

diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index d31fb82..ad72353 100644 (file)
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2022 NXP
  */
 
 #include <common.h>
@@ -114,11 +115,6 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
                fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       if (sec_init() < 0)
-               fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
-#endif
-
 /*
  * dm_init_and_scan() is called as part of common SPL framework, so no
  * need to call it again but in case of powerpc platforms which currently

diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index f56e4e8..7a23d8f 100644 (file)
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2022 NXP
  */
 
 #include <common.h>
@@ -19,6 +19,7 @@
 #ifdef CONFIG_ARCH_LS1021A
 #include <asm/arch/immap_ls102xa.h>
 #endif
+#include <dm/lists.h>
 
 #define SHA256_BITS    256
 #define SHA256_BYTES   (256/8)
@@ -807,6 +808,13 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
        prop.num_bits = key_len * 8;
        prop.exp_len = key_len;
 
+#if defined(CONFIG_SPL_BUILD)
+       ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL);
+       if (ret) {
+               printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret);
+               return -EINVAL;
+       }
+#endif
        ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
        if (ret) {
                printf("RSA: Can't find Modular Exp implementation\n");

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index a3aa84d..746b35a 100644 (file)
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019, 2021 NXP
+ * Copyright 2019, 2021-2022 NXP
  */
 
 #include <common.h>
@@ -34,7 +34,7 @@
 #include <fsl_qe.h>
 #endif
 #include <fsl_validate.h>
-
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -530,6 +530,15 @@ int board_init(void)
 #if defined(CONFIG_SPL_BUILD)
 void spl_board_init(void)
 {
+       if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+               struct udevice *dev;
+               int ret;
+
+               ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+               if (ret)
+                       printf("Failed to initialize caam_jr: %d\n", ret);
+       }
+
        ls102xa_smmu_stream_id_init();
 }
 #endif

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 002869f..f388eb4 100644 (file)
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2022 NXP
  */
 
 #include <common.h>
@@ -272,6 +272,39 @@ void fdt_del_qe(void *blob)
        }
 }
 
+/* Update the address of the Aquantia PHY on the MDIO bus for boards revision
+ * v7.0 and up. Also rename the PHY node to align with the address change.
+ */
+void fdt_fixup_phy_addr(void *blob)
+{
+       const char phy_path[] =
+               "/soc/fman@1a00000/mdio@fd000/ethernet-phy@1";
+       int ret, offset, new_addr = AQR113C_PHY_ADDR;
+       char new_name[] = "ethernet-phy@00";
+
+       if (CPLD_READ(pcba_ver) < 0x7)
+               return;
+
+       offset = fdt_path_offset(blob, phy_path);
+       if (offset < 0) {
+               printf("ethernet-phy@1 node not found in the dts\n");
+               return;
+       }
+
+       ret = fdt_setprop_u32(blob, offset, "reg", new_addr);
+       if (ret < 0) {
+               printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
+                      fdt_strerror(ret));
+               return;
+       }
+
+       sprintf(new_name, "ethernet-phy@%x", new_addr);
+       ret = fdt_set_name(blob, offset, new_name);
+       if (ret < 0)
+               printf("Unable to rename node ethernet-phy@1: %s\n",
+                      fdt_strerror(ret));
+}
+
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
        u64 base[CONFIG_NR_DRAM_BANKS];
@@ -290,6 +323,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifndef CONFIG_DM_ETH
        fdt_fixup_fman_ethernet(blob);
 #endif
+       fdt_fixup_phy_addr(blob);
 #endif
 
        fdt_fixup_icid(blob);
@@ -313,6 +347,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
        return 0;
 }
 
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+       fdt_fixup_phy_addr(blob);
+       return 0;
+}
+#endif
+
 u8 flash_read8(void *addr)
 {
        return __raw_readb(addr + 1);

diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 0a40bf0..cc06756 100644 (file)
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FSL_LS_PPA=y
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y

diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index f27eadf..7b6080e 100644 (file)
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -14,6 +14,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index da23382..8347407 100644 (file)
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@ CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y

diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 2be08bb..5402fbb 100644 (file)
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -19,6 +19,7 @@ CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index d9b841d..baac67f 100644 (file)
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -15,6 +15,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y

diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 79feb55..ee9b886 100644 (file)
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -20,6 +20,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 3aafd10..1adf265 100644 (file)
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_NXP_ESBC=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y

diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index f9cb304..78a383b 100644 (file)
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x60500000
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index d36b2c7..ff5da5d 100644 (file)
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2015 Freescale Semiconductor
+ * Copyright 2022 NXP
  */
 
 #ifndef __LS1043ARDB_H__
@@ -206,7 +207,9 @@
 #define QSGMII_PORT3_PHY_ADDR          0x6
 #define QSGMII_PORT4_PHY_ADDR          0x7
 
-#define FM1_10GEC1_PHY_ADDR            0x1
+/* The AQR PHY model and MDIO address differ between board revisions */
+#define FM1_10GEC1_PHY_ADDR            0x1 /* AQR105 on boards up to v6.0 */
+#define AQR113C_PHY_ADDR               0x8 /* AQR113C on boards v7.0 and up */
 #endif
 #endif