struct perf_event *event = cpuc->events[0]; /* PMC0 only */
struct pebs_record_core *at, *top;
struct perf_sample_data data;
- struct perf_raw_record raw;
struct pt_regs regs;
int n;
perf_sample_data_init(&data, 0);
data.period = event->hw.last_period;
- if (event->attr.sample_type & PERF_SAMPLE_RAW) {
- raw.size = x86_pmu.pebs_record_size;
- raw.data = at;
- data.raw = &raw;
- }
-
/*
* We use the interrupt regs as a base because the PEBS record
* does not contain a full regs set, specifically it seems to
struct pebs_record_nhm *at, *top;
struct perf_sample_data data;
struct perf_event *event = NULL;
- struct perf_raw_record raw;
struct pt_regs regs;
u64 status = 0;
int bit, n;
perf_sample_data_init(&data, 0);
data.period = event->hw.last_period;
- if (event->attr.sample_type & PERF_SAMPLE_RAW) {
- raw.size = x86_pmu.pebs_record_size;
- raw.data = at;
- data.raw = &raw;
- }
-
/*
* See the comment in intel_pmu_drain_pebs_core()
*/