juno: add untuned C-state details to device tree
authorSudeep Holla <sudeep.holla@arm.com>
Wed, 4 Jun 2014 15:22:35 +0000 (16:22 +0100)
committerSudeep Holla <sudeep.holla@arm.com>
Wed, 4 Jun 2014 15:49:13 +0000 (16:49 +0100)
Also add hack to workaround mmaped timer access issue

arch/arm64/boot/dts/juno.dts
arch/arm64/configs/defconfig
drivers/clocksource/arm_arch_timer.c

index 81e5675..c69a7bd 100644 (file)
                        };
                };
 
+               idle-states {
+                       entry-method = "arm,psci";
+
+                       CPU_SLEEP_0: cpu-sleep-0 {
+                               compatible = "arm,idle-state";
+                               entry-method-param = <0x0010000>;
+                               entry-latency-us = <40>;
+                               exit-latency-us = <100>;
+                               min-residency-us = <150>;
+                       };
+
+                       CLUSTER_SLEEP_0: cluster-sleep-0 {
+                               compatible = "arm,idle-state";
+                               entry-method-param = <0x1010000>;
+                               entry-latency-us = <500>;
+                               exit-latency-us = <1000>;
+                               min-residency-us = <2500>;
+                       };
+               };
+
                CPU0:cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53","arm,armv8";
@@ -55,6 +75,7 @@
                        enable-method = "psci";
                        clocks = <&scpi_dvfs 1>;
                        clock-names = "vlittle";
+                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
                CPU1:cpu@101 {
@@ -64,6 +85,7 @@
                        enable-method = "psci";
                        clocks = <&scpi_dvfs 1>;
                        clock-names = "vlittle";
+                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
                CPU2:cpu@102 {
@@ -73,6 +95,7 @@
                        enable-method = "psci";
                        clocks = <&scpi_dvfs 1>;
                        clock-names = "vlittle";
+                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
                CPU3:cpu@103 {
                        enable-method = "psci";
                        clocks = <&scpi_dvfs 1>;
                        clock-names = "vlittle";
+                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
                CPU4:cpu@0 {
                        enable-method = "psci";
                        clocks = <&scpi_dvfs 0>;
                        clock-names = "vbig";
+                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
 
                CPU5:cpu@1 {
                        enable-method = "psci";
                        clocks = <&scpi_dvfs 0>;
                        clock-names = "vbig";
+                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                };
        };
 
                             <1 10 0xff01>;
        };
 
+       timer@2a810000 {
+               compatible = "arm,armv7-timer-mem";
+               reg = <0x0 0x2a810000 0x0 0x10000>;
+               clock-frequency = <100000000>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               frame@2a830000 {
+                       frame-number = <1>;
+                       interrupts = <0 60 4>;
+                       reg = <0x0 0x2a830000 0x0 0x10000>;
+               };
+       };
+
        pmu {
                compatible = "arm,armv8-pmuv3";
-               interrupts = <0 60 4>,
-                            <0 61 4>,
-                            <0 62 4>,
-                            <0 63 4>;
+               interrupts = <0 18 4>,
+                            <0 22 4>,
+                            <0 26 4>,
+                            <0 30 4>,
+                            <0 02 4>,
+                            <0 06 4>;
        };
 
        psci {
index 0e85b9c..fa2c3c9 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_PM_ADVANCED_DEBUG=y
 CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
 CONFIG_CPU_IDLE=y
 CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_ARM64_CPUIDLE=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_STAT_DETAILS=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
index 5163ec1..c391b67 100644 (file)
@@ -683,6 +683,7 @@ static void __init arch_timer_mem_init(struct device_node *np)
        u32 cnttidr;
 
        arch_timers_present |= ARCH_MEM_TIMER;
+       /*
        cntctlbase = of_iomap(np, 0);
        if (!cntctlbase) {
                pr_err("arch_timer: Can't find CNTCTLBase\n");
@@ -691,7 +692,8 @@ static void __init arch_timer_mem_init(struct device_node *np)
 
        cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
        iounmap(cntctlbase);
-
+       */
+       cnttidr = 0x1;
        /*
         * Try to find a virtual capable frame. Otherwise fall back to a
         * physical capable frame.