}
}
-int
-crocus_reg_read(struct crocus_bufmgr *bufmgr, uint32_t offset, uint64_t *result)
-{
- struct drm_i915_reg_read reg_read = { .offset = offset };
- int ret = intel_ioctl(bufmgr->fd, DRM_IOCTL_I915_REG_READ, ®_read);
-
- *result = reg_read.val;
- return ret;
-}
-
static int
gem_param(int fd, int name)
{
uint32_t crocus_bo_export_gem_handle(struct crocus_bo *bo);
-int crocus_reg_read(struct crocus_bufmgr *bufmgr, uint32_t offset,
- uint64_t *out);
-
int drm_ioctl(int fd, unsigned long request, void *arg);
#endif /* CROCUS_BUFMGR_H */
crocus_get_timestamp(struct pipe_screen *pscreen)
{
struct crocus_screen *screen = (struct crocus_screen *) pscreen;
- const unsigned TIMESTAMP = 0x2358;
uint64_t result;
- crocus_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
+ if (!intel_gem_read_render_timestamp(crocus_bufmgr_get_fd(screen->bufmgr),
+ &result))
+ return 0;
result = intel_device_info_timebase_scale(&screen->devinfo, result);
result &= (1ull << TIMESTAMP_BITS) - 1;
}
}
-int
-iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *result)
-{
- struct drm_i915_reg_read reg_read = { .offset = offset };
- int ret = intel_ioctl(bufmgr->fd, DRM_IOCTL_I915_REG_READ, ®_read);
-
- *result = reg_read.val;
- return ret;
-}
-
static struct intel_buffer *
intel_aux_map_buffer_alloc(void *driver_ctx, uint32_t size)
{
uint32_t iris_bo_export_gem_handle(struct iris_bo *bo);
-int iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *out);
-
/**
* Returns the BO's address relative to the appropriate base address.
*
iris_get_timestamp(struct pipe_screen *pscreen)
{
struct iris_screen *screen = (struct iris_screen *) pscreen;
- const unsigned TIMESTAMP = 0x2358;
uint64_t result;
- iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
+ if (!intel_gem_read_render_timestamp(iris_bufmgr_get_fd(screen->bufmgr),
+ &result))
+ return 0;
result = intel_device_info_timebase_scale(&screen->devinfo, result);
result &= (1ull << TIMESTAMP_BITS) - 1;
#include "intel_gem.h"
#include "drm-uapi/i915_drm.h"
+#define RCS_TIMESTAMP 0x2358
+
bool
intel_gem_supports_syncobj_wait(int fd)
{
return create.ctx_id;
}
+
+bool intel_gem_read_render_timestamp(int fd, uint64_t *value)
+{
+ struct drm_i915_reg_read reg_read = {
+ .offset = RCS_TIMESTAMP | I915_REG_READ_8B_WA,
+ };
+
+ int ret = intel_ioctl(fd, DRM_IOCTL_I915_REG_READ, ®_read);
+ if (ret == 0)
+ *value = reg_read.val;
+ return ret == 0;
+}
#ifndef INTEL_GEM_H
#define INTEL_GEM_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
#include "drm-uapi/i915_drm.h"
#include <assert.h>
return ret;
}
-static inline uint64_t
-intel_read_gpu_timestamp(int fd)
-{
- struct drm_i915_reg_read reg_read = {};
- const uint64_t render_ring_timestamp = 0x2358;
- reg_read.offset = render_ring_timestamp | I915_REG_READ_8B_WA;
-
- if (intel_ioctl(fd, DRM_IOCTL_I915_REG_READ, ®_read) < 0)
- return 0;
-
- return reg_read.val;
-}
-
/**
* A wrapper around DRM_IOCTL_I915_QUERY
*
const struct drm_i915_query_engine_info *info,
int num_engines, uint16_t *engine_classes);
+bool intel_gem_read_render_timestamp(int fd, uint64_t *value);
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* INTEL_GEM_H */
struct intel_ds_device *device)
{
uint64_t cpu_ts = perfetto::base::GetBootTimeNs().count();
- uint64_t gpu_ts = intel_device_info_timebase_scale(&device->info,
- intel_read_gpu_timestamp(device->fd));
+ uint64_t gpu_ts;
+ intel_gem_read_render_timestamp(device->fd, &gpu_ts);
+ gpu_ts = intel_device_info_timebase_scale(&device->info, gpu_ts);
if (cpu_ts < device->next_clock_sync_ns)
return;
{
this->sampling_period_ns = sampling_period_ns;
- gpu_timestamp_udw = intel_read_gpu_timestamp(drm_device.fd) & ~perf->cfg->oa_timestamp_mask;
+ intel_gem_read_render_timestamp(drm_device.fd, &gpu_timestamp_udw);
+ gpu_timestamp_udw &= ~perf->cfg->oa_timestamp_mask;
if (!perf->open(sampling_period_ns, selected_query)) {
PPS_LOG_FATAL("Failed to open intel perf");
}
* do it now. If we see a roll over the lower 32bits capture it
* again.
*/
- if (gpu_timestamp_udw == 0 || (gpu_timestamp_udw | gpu_timestamp_ldw) < last_gpu_timestamp)
- gpu_timestamp_udw = intel_read_gpu_timestamp(drm_device.fd) & ~perf->cfg->oa_timestamp_mask;
+ if (gpu_timestamp_udw == 0 ||
+ (gpu_timestamp_udw | gpu_timestamp_ldw) < last_gpu_timestamp) {
+ intel_gem_read_render_timestamp(drm_device.fd, &gpu_timestamp_udw);
+ gpu_timestamp_udw &= ~perf->cfg->oa_timestamp_mask;
+ }
uint64_t gpu_timestamp = gpu_timestamp_udw | gpu_timestamp_ldw;
uint64_t IntelDriver::gpu_timestamp() const
{
- return intel_device_info_timebase_scale(&perf->devinfo,
- intel_read_gpu_timestamp(drm_device.fd));
+ uint64_t timestamp;
+ intel_gem_read_render_timestamp(drm_device.fd, ×tamp);
+ return intel_device_info_timebase_scale(&perf->devinfo, timestamp);
}
} // namespace pps
'intel-driver-ds',
sources : ['intel_driver_ds.cc', intel_tracepoint_files],
include_directories : [inc_src, inc_include, inc_intel, inc_mapi, inc_mesa],
- link_with : [libintel_perf, libintel_dev],
+ link_with : [libintel_perf, libintel_dev, libintel_common],
dependencies : libintel_driver_ds_deps,
override_options : ['cpp_std=c++17'],
gnu_symbol_visibility : 'hidden',
'pps-intel',
sources: pps_intel_sources,
include_directories: [inc_tool, inc_src, inc_include, inc_intel],
- link_with: [libintel_perf, libintel_dev],
+ link_with: [libintel_perf, libintel_dev, libintel_common],
dependencies: [dep_perfetto, dep_libdrm, idep_mesautil],
override_options: ['cpp_std=c++17']
)
*/
#define MAX_DEBUG_MESSAGE_LENGTH 4096
-/* Render engine timestamp register */
-#define TIMESTAMP 0x2358
-
/* The "RAW" clocks on Linux are called "FAST" on FreeBSD */
#if !defined(CLOCK_MONOTONIC_RAW) && defined(CLOCK_MONOTONIC_FAST)
#define CLOCK_MONOTONIC_RAW CLOCK_MONOTONIC_FAST
/* Check if we can read the GPU timestamp register from the CPU */
uint64_t u64_ignore;
- device->has_reg_timestamp = anv_gem_reg_read(fd, TIMESTAMP | I915_REG_READ_8B_WA,
- &u64_ignore) == 0;
+ device->has_reg_timestamp = intel_gem_read_render_timestamp(fd, &u64_ignore);
device->always_flush_cache = INTEL_DEBUG(DEBUG_STALL) ||
driQueryOptionb(&instance->dri_options, "always_flush_cache");
{
ANV_FROM_HANDLE(anv_device, device, _device);
uint64_t timestamp_frequency = device->info->timestamp_frequency;
- int ret;
int d;
uint64_t begin, end;
uint64_t max_clock_period = 0;
for (d = 0; d < timestampCount; d++) {
switch (pTimestampInfos[d].timeDomain) {
case VK_TIME_DOMAIN_DEVICE_EXT:
- ret = anv_gem_reg_read(device->fd, TIMESTAMP | I915_REG_READ_8B_WA,
- &pTimestamps[d]);
-
- if (ret != 0) {
+ if (!intel_gem_read_render_timestamp(device->fd, &pTimestamps[d])) {
return vk_device_set_lost(&device->vk, "Failed to read the "
"TIMESTAMP register: %m");
}
return args.handle;
}
-int
-anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result)
-{
- struct drm_i915_reg_read args = {
- .offset = offset
- };
-
- int ret = intel_ioctl(fd, DRM_IOCTL_I915_REG_READ, &args);
-
- *result = args.val;
- return ret;
-}
-
struct drm_i915_query_engine_info *
anv_gem_get_engine_info(int fd)
{
{
unreachable("Unused");
}
-
-int
-anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result)
-{
- unreachable("Unused");
-}
int anv_gem_context_get_reset_stats(int fd, int context,
uint32_t *active, uint32_t *pending);
int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
-int anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result);
uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
int anv_i915_query(int fd, uint64_t query_id, void *buffer,
/* Check if we can read the GPU timestamp register from the CPU */
uint64_t u64_ignore;
- device->has_reg_timestamp = anv_gem_reg_read(fd, TIMESTAMP | I915_REG_READ_8B_WA,
- &u64_ignore) == 0;
+ device->has_reg_timestamp = intel_gem_read_render_timestamp(fd, &u64_ignore);
device->always_flush_cache = INTEL_DEBUG(DEBUG_STALL) ||
driQueryOptionb(&instance->dri_options, "always_flush_cache");
{
ANV_FROM_HANDLE(anv_device, device, _device);
uint64_t timestamp_frequency = device->info->timestamp_frequency;
- int ret;
int d;
uint64_t begin, end;
uint64_t max_clock_period = 0;
for (d = 0; d < timestampCount; d++) {
switch (pTimestampInfos[d].timeDomain) {
case VK_TIME_DOMAIN_DEVICE_EXT:
- ret = anv_gem_reg_read(device->fd, TIMESTAMP | I915_REG_READ_8B_WA,
- &pTimestamps[d]);
-
- if (ret != 0) {
+ if (!intel_gem_read_render_timestamp(device->fd, &pTimestamps[d])) {
return vk_device_set_lost(&device->vk, "Failed to read the "
"TIMESTAMP register: %m");
}
return args.handle;
}
-int
-anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result)
-{
- struct drm_i915_reg_read args = {
- .offset = offset
- };
-
- int ret = intel_ioctl(fd, DRM_IOCTL_I915_REG_READ, &args);
-
- *result = args.val;
- return ret;
-}
-
struct drm_i915_query_engine_info *
anv_gem_get_engine_info(int fd)
{
{
unreachable("Unused");
}
-
-int
-anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result)
-{
- unreachable("Unused");
-}
int anv_gem_context_get_reset_stats(int fd, int context,
uint32_t *active, uint32_t *pending);
int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
-int anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result);
uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
int anv_i915_query(int fd, uint64_t query_id, void *buffer,