drm/amd/display: update pixel format in DP hw sequence

[WHY]
DP 420 formats do not light up because the pixel processing mode
of the DP_FORMAT is misprogrammed

[HOW]
Added appropriate programming for DP pixel format

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Yihan Zhu <yihan.zhu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
index 962a2c02b422a23e7ca137def5f3da23e927f10c..742e43cb8880dfc8e57fe2d669709205a4639c9b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
@@ -296,12 +296,14 @@ static void enc314_stream_encoder_dp_unblank(
                uint32_t n_vid = 0x8000;
                uint32_t m_vid;
                uint32_t n_multiply = 0;
+               uint32_t pix_per_cycle = 0;
                uint64_t m_vid_l = n_vid;
 
                /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
                if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {
                        /*this logic should be the same in get_pixel_clock_parameters() */
                        n_multiply = 1;
+                       pix_per_cycle = 1;
                }
                /* M / N = Fstream / Flink
                 * m_vid / n_vid = pixel rate / link rate
@@ -329,6 +331,10 @@ static void enc314_stream_encoder_dp_unblank(
                REG_UPDATE_2(DP_VID_TIMING,
                                DP_VID_M_N_GEN_EN, 1,
                                DP_VID_N_MUL, n_multiply);
+
+               REG_UPDATE(DP_PIXEL_FORMAT,
+                               DP_PIXEL_PER_CYCLE_PROCESSING_MODE,
+                               pix_per_cycle);
        }
 
        /* make sure stream is disabled before resetting steer fifo */