config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
} else {
- bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
+ bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
*/
if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
vgpr_comp_cnt = 3;
- } else if (info->vs.export_prim_id) {
+ } else if (info->vs.outinfo.export_prim_id) {
vgpr_comp_cnt = 2;
} else if (info->vs.needs_instance_id) {
vgpr_comp_cnt = 1;
if (es_stage == MESA_SHADER_VERTEX) {
es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
} else if (es_stage == MESA_SHADER_TESS_EVAL) {
- bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
+ bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
} else
unreachable("Unexpected ES shader stage");
struct radv_es_output_info es_info;
bool as_es;
bool as_ls;
- bool export_prim_id;
bool tcs_in_out_eq;
uint64_t tcs_temp_only_input_mask;
uint8_t num_linked_outputs;
enum gl_tess_spacing spacing;
bool ccw;
bool point_mode;
- bool export_prim_id;
uint8_t num_linked_inputs;
uint8_t num_linked_patch_inputs;
uint8_t num_linked_outputs;
info->tes.ccw = nir->info.tess.ccw;
info->tes.point_mode = nir->info.tess.point_mode;
info->tes.as_es = key->vs_common_out.as_es;
- info->tes.export_prim_id = key->vs_common_out.export_prim_id;
info->is_ngg = key->vs_common_out.as_ngg;
info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough;
break;
case MESA_SHADER_VERTEX:
info->vs.as_es = key->vs_common_out.as_es;
info->vs.as_ls = key->vs_common_out.as_ls;
- info->vs.export_prim_id = key->vs_common_out.export_prim_id;
info->is_ngg = key->vs_common_out.as_ngg;
info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough;
break;