drm/bridge/sii8620: abstract out sink detection code

MHL1 and MHL3 have different initialization paths. To make both protocols
happy sink detection is put into continuation after link mode enablement.

Change-Id: I739fd47dce782b151e9a498364ed42de9223996b
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 853b73f1d131fb0d6dd594dec0e12922b4b0f7b3..56762412192fb37694c366ced8a571a4d96f74d1 100644 (file)
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -406,7 +406,7 @@ static void sii8620_update_array(u8 *dst, u8 *src, int count)
        }
 }
 
-static void sii8620_mr_devcap(struct sii8620 *ctx)
+static void sii8620_sink_detected(struct sii8620 *ctx, int ret)
 {
        static const char * const sink_str[] = {
                [SINK_NONE] = "NONE",
@@ -414,22 +414,8 @@ static void sii8620_mr_devcap(struct sii8620 *ctx)
                [SINK_DVI] = "DVI"
        };
 
-       u8 dcap[MHL_DCAP_SIZE];
        struct device *dev = ctx->dev;
 
-       sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
-       if (ctx->error < 0)
-               return;
-
-       dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
-               dcap[MHL_DCAP_MHL_VERSION] / 16, dcap[MHL_DCAP_MHL_VERSION] % 16,
-               dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L],
-               dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]);
-       sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
-
-       if (!(dcap[MHL_DCAP_CAT] & MHL_DCAP_CAT_SINK))
-               return;
-
        sii8620_fetch_edid(ctx);
        if (!ctx->edid) {
                dev_err(ctx->dev, "Cannot fetch EDID\n");
@@ -447,6 +433,22 @@ static void sii8620_mr_devcap(struct sii8620 *ctx)
        sii8620_enable_hpd(ctx);
 }
 
+static void sii8620_mr_devcap(struct sii8620 *ctx)
+{
+       u8 dcap[MHL_DCAP_SIZE];
+       struct device *dev = ctx->dev;
+
+       sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
+       if (ctx->error < 0)
+               return;
+
+       dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
+               dcap[MHL_DCAP_MHL_VERSION] / 16, dcap[MHL_DCAP_MHL_VERSION] % 16,
+               dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L],
+               dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]);
+       sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
+}
+
 static void sii8620_mr_xdevcap(struct sii8620 *ctx)
 {
        sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap,
@@ -1406,6 +1408,7 @@ static void sii8620_status_changed_path(struct sii8620 *ctx)
                                      | MHL_DST_LM_PATH_ENABLED);
                if (ctx->mode < CM_MHL3)
                        sii8620_mt_read_devcap(ctx, false);
+               sii8620_mt_set_cont(ctx, sii8620_sink_detected);
        } else {
                sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
                                      MHL_DST_LM_CLK_MODE_NORMAL);