RISC-V: Add StarFive JH7100 audio reset node

Add device tree node for the audio resets on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 0b948f6..9f387fd 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -144,6 +144,12 @@
                        #clock-cells = <1>;
                };
 
+               audrst: reset-controller@10490000 {
+                       compatible = "starfive,jh7100-audrst";
+                       reg = <0x0 0x10490000 0x0 0x10000>;
+                       #reset-cells = <1>;
+               };
+
                clkgen: clock-controller@11800000 {
                        compatible = "starfive,jh7100-clkgen";
                        reg = <0x0 0x11800000 0x0 0x10000>;