#include "i965_encoder.h"
static void
-gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen6_mfc_pipe_mode_select(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
BEGIN_BCS_BATCH(batch, 4);
static void
gen7_mfc_pipe_mode_select(VADriverContextP ctx,
int standard_select,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
assert(standard_select == MFX_FORMAT_MPEG2 ||
standard_select == MFX_FORMAT_AVC);
}
static void
-gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen6_mfc_surface_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 6);
OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
}
static void
-gen7_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen7_mfc_surface_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 6);
OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
}
static void
-gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 24);
OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
}
static void
-gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 11);
OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
}
static void
-gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 11);
OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
}
static void
-gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 4);
OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
}
static void
-gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen6_mfc_avc_img_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
-
int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 13);
OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
OUT_BCS_BATCH(batch,
}
static void
-gen7_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen7_mfc_avc_img_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
-
int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 16);
OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
OUT_BCS_BATCH(batch,
ADVANCE_BCS_BATCH(batch);
}
-static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_mfc_avc_directmode_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 69);
OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
int intra_slice,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 11);;
OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
ADVANCE_BCS_BATCH(batch);
}
-static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 58);
OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
ADVANCE_BCS_BATCH(batch);
}
-static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_mfc_avc_fqm_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 113);
OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
int qm_type,
unsigned int *qm,
int qm_length,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
unsigned int qm_buffer[16];
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
assert(qm_length <= 16);
assert(sizeof(*qm) == 4);
memcpy(qm_buffer, qm, qm_length * 4);
ADVANCE_BCS_BATCH(batch);
}
-static void gen7_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen7_mfc_avc_qm_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
unsigned int qm[16] = {
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010
};
- gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context);
- gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context);
- gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context);
- gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context);
+ gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context, batch);
+ gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context, batch);
+ gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context, batch);
+ gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context, batch);
}
static void
int fqm_type,
unsigned int *fqm,
int fqm_length,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
unsigned int fqm_buffer[32];
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
assert(fqm_length <= 32);
assert(sizeof(*fqm) == 4);
memcpy(fqm_buffer, fqm, fqm_length * 4);
ADVANCE_BCS_BATCH(batch);
}
-static void gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen7_mfc_avc_fqm_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
unsigned int qm[32] = {
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000
};
- gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context);
- gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context);
- gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context);
- gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context);
+ gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context, batch);
+ gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context, batch);
+ gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context, batch);
+ gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context, batch);
}
-static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 10);
OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
}
static void
-gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data, struct gen6_encoder_context *gen6_encoder_context)
+gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
BEGIN_BCS_BATCH(batch, 4);
static int
gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int len_in_dwords = 11;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, len_in_dwords);
OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
}
static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context, struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int len_in_dwords = 11;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, len_in_dwords);
OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
intel_batchbuffer_emit_mi_flush(batch);
if (IS_GEN7(i965->intel.device_id)) {
- gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context);
- gen7_mfc_surface_state(ctx, gen6_encoder_context);
- gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
+ gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context, batch);
+ gen7_mfc_surface_state(ctx, gen6_encoder_context, batch);
+ gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context, batch);
} else {
- gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context);
- gen6_mfc_surface_state(ctx, gen6_encoder_context);
- gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
+ gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context, batch);
+ gen6_mfc_surface_state(ctx, gen6_encoder_context, batch);
+ gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context, batch);
}
- gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
- gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context);
+ gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context, batch);
+ gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context, batch);
if (IS_GEN7(i965->intel.device_id)) {
- gen7_mfc_avc_img_state(ctx, gen6_encoder_context);
- gen7_mfc_avc_qm_state(ctx, gen6_encoder_context);
- gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context);
+ gen7_mfc_avc_img_state(ctx, gen6_encoder_context, batch);
+ gen7_mfc_avc_qm_state(ctx, gen6_encoder_context, batch);
+ gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context, batch);
} else {
- gen6_mfc_avc_img_state(ctx, gen6_encoder_context);
- gen6_mfc_avc_qm_state(ctx, gen6_encoder_context);
- gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context);
+ gen6_mfc_avc_img_state(ctx, gen6_encoder_context, batch);
+ gen6_mfc_avc_qm_state(ctx, gen6_encoder_context, batch);
+ gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context, batch);
}
- gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context);
- gen6_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context);
+ gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context, batch);
+ gen6_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context, batch);
emit_new_state = 0;
}
if (is_intra) {
assert(msg);
- object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context);
+ object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context, batch);
msg += 4;
} else {
- object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context);
+ object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context, batch);
offset += 64;
}
return VA_STATUS_SUCCESS;
}
-static void gen6_vme_pipeline_select(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_vme_pipeline_select(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
BEGIN_BATCH(batch, 1);
OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
ADVANCE_BATCH(batch);
}
-static void gen6_vme_state_base_address(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_vme_state_base_address(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
BEGIN_BATCH(batch, 10);
ADVANCE_BATCH(batch);
}
-static void gen6_vme_vfe_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_vme_vfe_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, 8);
OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | 6); /*Gen6 CMD_MEDIA_STATE_POINTERS = CMD_MEDIA_STATE */
}
-static void gen6_vme_curbe_load(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_vme_curbe_load(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, 4);
OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | 2);
ADVANCE_BATCH(batch);
}
-static void gen6_vme_idrt(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen6_vme_idrt(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, 4);
OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | 2);
struct encode_state *encode_state,
int mb_x, int mb_y,
int kernel,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
int mb_width = ALIGN(obj_surface->orig_width, 16) / 16;
int len_in_dowrds = 6 + 1;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, len_in_dowrds);
OUT_BATCH(batch, CMD_MEDIA_OBJECT | (len_in_dowrds - 2));
intel_batchbuffer_emit_mi_flush(batch);
/*Step2: State command PIPELINE_SELECT*/
- gen6_vme_pipeline_select(ctx, gen6_encoder_context);
+ gen6_vme_pipeline_select(ctx, gen6_encoder_context, batch);
/*Step3: State commands configuring pipeline states*/
- gen6_vme_state_base_address(ctx, gen6_encoder_context);
- gen6_vme_vfe_state(ctx, gen6_encoder_context);
- gen6_vme_curbe_load(ctx, gen6_encoder_context);
- gen6_vme_idrt(ctx, gen6_encoder_context);
+ gen6_vme_state_base_address(ctx, gen6_encoder_context, batch);
+ gen6_vme_vfe_state(ctx, gen6_encoder_context, batch);
+ gen6_vme_curbe_load(ctx, gen6_encoder_context, batch);
+ gen6_vme_idrt(ctx, gen6_encoder_context, batch);
emit_new_state = 0;
}
/*Step4: Primitive commands*/
- object_len_in_bytes = gen6_vme_media_object(ctx, encode_state, x, y, is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER, gen6_encoder_context);
+ object_len_in_bytes = gen6_vme_media_object(ctx, encode_state, x, y, is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER, gen6_encoder_context, batch);
if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
assert(0);
static void
gen75_mfc_pipe_mode_select(VADriverContextP ctx,
- int standard_select,
- struct gen6_encoder_context *gen6_encoder_context)
+ int standard_select,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
assert(standard_select == MFX_FORMAT_MPEG2 ||
standard_select == MFX_FORMAT_AVC);
static void
-gen75_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen75_mfc_surface_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 6);
OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
static void
gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 61);
OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
}
static void
-gen75_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen75_mfc_pipe_buf_addr_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
int i;
-
struct i965_driver_data *i965 = i965_driver_data(ctx);
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_pipe_buf_addr_state_bplus(ctx, gen6_encoder_context);
+ gen75_mfc_pipe_buf_addr_state_bplus(ctx, gen6_encoder_context, batch);
return;
}
static void
gen75_mfc_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 26);
OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
}
static void
-gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
struct i965_driver_data *i965 = i965_driver_data(ctx);
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_ind_obj_base_addr_state_bplus(ctx, gen6_encoder_context);
+ gen75_mfc_ind_obj_base_addr_state_bplus(ctx, gen6_encoder_context, batch);
return;
}
static void
gen75_mfc_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 10);
OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
}
static void
-gen75_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen75_mfc_bsp_buf_base_addr_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
struct i965_driver_data *i965 = i965_driver_data(ctx);
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_bsp_buf_base_addr_state_bplus(ctx, gen6_encoder_context);
+ gen75_mfc_bsp_buf_base_addr_state_bplus(ctx, gen6_encoder_context, batch);
return;
}
}
static void
-gen75_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+gen75_mfc_avc_img_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
-
int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 16);
OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
OUT_BCS_BATCH(batch,
static void
gen75_mfc_avc_directmode_state_bplus(VADriverContextP ctx,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
-
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 71);
OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
ADVANCE_BCS_BATCH(batch);
}
-static void gen75_mfc_avc_directmode_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_mfc_avc_directmode_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
int i;
struct i965_driver_data *i965 = i965_driver_data(ctx);
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
if (IS_STEPPING_BPLUS(i965)) {
- gen75_mfc_avc_directmode_state_bplus(ctx, gen6_encoder_context);
+ gen75_mfc_avc_directmode_state_bplus(ctx, gen6_encoder_context, batch);
return;
}
}
static void gen75_mfc_avc_slice_state(VADriverContextP ctx,
- int intra_slice,
- struct gen6_encoder_context *gen6_encoder_context)
+ int intra_slice,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 11);;
OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
static void
gen75_mfc_qm_state(VADriverContextP ctx,
- int qm_type,
- unsigned int *qm,
- int qm_length,
- struct gen6_encoder_context *gen6_encoder_context)
+ int qm_type,
+ unsigned int *qm,
+ int qm_length,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
unsigned int qm_buffer[16];
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
assert(qm_length <= 16);
assert(sizeof(*qm) == 4);
memcpy(qm_buffer, qm, qm_length * 4);
ADVANCE_BCS_BATCH(batch);
}
-static void gen75_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_mfc_avc_qm_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
unsigned int qm[16] = {
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010
};
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context);
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context);
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context);
- gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context);
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context, batch);
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context, batch);
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context, batch);
+ gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context, batch);
}
static void
gen75_mfc_fqm_state(VADriverContextP ctx,
- int fqm_type,
- unsigned int *fqm,
- int fqm_length,
- struct gen6_encoder_context *gen6_encoder_context)
+ int fqm_type,
+ unsigned int *fqm,
+ int fqm_length,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
unsigned int fqm_buffer[32];
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
assert(fqm_length <= 32);
assert(sizeof(*fqm) == 4);
memcpy(fqm_buffer, fqm, fqm_length * 4);
ADVANCE_BCS_BATCH(batch);
}
-static void gen75_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_mfc_avc_fqm_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
unsigned int qm[32] = {
0x10001000, 0x10001000, 0x10001000, 0x10001000,
0x10001000, 0x10001000, 0x10001000, 0x10001000
};
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context);
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context);
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context);
- gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context);
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context, batch);
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context, batch);
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context, batch);
+ gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context, batch);
}
-static void gen75_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_mfc_avc_ref_idx_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int i;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, 10);
OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
}
static void
-gen75_mfc_avc_insert_object(VADriverContextP ctx, int flush_data, struct gen6_encoder_context *gen6_encoder_context)
+gen75_mfc_avc_insert_object(VADriverContextP ctx, int flush_data,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
BEGIN_BCS_BATCH(batch, 4);
static int
gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int len_in_dwords = 12;
unsigned int intra_msg;
#define INTRA_MSG_FLAG (1 << 13)
#define INTRA_MBTYPE_MASK (0x1F0000)
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, len_in_dwords);
intra_msg = msg[0] & 0xC0FF;
}
static int gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
- unsigned int offset, unsigned int *msg, struct gen6_encoder_context *gen6_encoder_context)
+ unsigned int offset, unsigned int *msg, struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
int len_in_dwords = 12;
unsigned int inter_msg;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BCS_BATCH(batch, len_in_dwords);
OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
if (emit_new_state) {
intel_batchbuffer_emit_mi_flush(batch);
- gen75_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context);
- gen75_mfc_surface_state(ctx, gen6_encoder_context);
- gen75_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
+ gen75_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context, batch);
+ gen75_mfc_surface_state(ctx, gen6_encoder_context, batch);
+ gen75_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context, batch);
- gen75_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
- gen75_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context);
+ gen75_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context, batch);
+ gen75_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context, batch);
- gen75_mfc_avc_img_state(ctx, gen6_encoder_context);
- gen75_mfc_avc_qm_state(ctx, gen6_encoder_context);
- gen75_mfc_avc_fqm_state(ctx, gen6_encoder_context);
- gen75_mfc_avc_directmode_state(ctx, gen6_encoder_context);
+ gen75_mfc_avc_img_state(ctx, gen6_encoder_context, batch);
+ gen75_mfc_avc_qm_state(ctx, gen6_encoder_context, batch);
+ gen75_mfc_avc_fqm_state(ctx, gen6_encoder_context, batch);
+ gen75_mfc_avc_directmode_state(ctx, gen6_encoder_context, batch);
- gen75_mfc_avc_ref_idx_state(ctx, gen6_encoder_context);
- gen75_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context);
+ gen75_mfc_avc_ref_idx_state(ctx, gen6_encoder_context, batch);
+ gen75_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context, batch);
emit_new_state = 0;
}
msg = (unsigned int *) (msg_ptr + mb_index * vme_context->vme_output.size_block);
if (is_intra) {
- object_len_in_bytes = gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context);
+ object_len_in_bytes = gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context, batch);
} else {
inter_rdo = msg[INTER_RDO_OFFSET] & RDO_MASK;
intra_rdo = msg[INTRA_RDO_OFFSET] & RDO_MASK;
if (intra_rdo < inter_rdo) {
- object_len_in_bytes = gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context);
+ object_len_in_bytes = gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context, batch);
} else {
- msg += INTER_MSG_OFFSET;
- offset = mb_index * vme_context->vme_output.size_block + INTER_MV_OFFSET;
- object_len_in_bytes = gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, msg, gen6_encoder_context);
+ msg += INTER_MSG_OFFSET;
+ offset = mb_index * vme_context->vme_output.size_block + INTER_MV_OFFSET;
+ object_len_in_bytes = gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, msg, gen6_encoder_context, batch);
}
}
if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
return VA_STATUS_SUCCESS;
}
-static void gen75_vme_pipeline_select(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_vme_pipeline_select(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
BEGIN_BATCH(batch, 1);
OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
ADVANCE_BATCH(batch);
}
-static void gen75_vme_state_base_address(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_vme_state_base_address(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
+
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
BEGIN_BATCH(batch, 10);
ADVANCE_BATCH(batch);
}
-static void gen75_vme_vfe_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_vme_vfe_state(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, 8);
OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | 6); /*Gen6 CMD_MEDIA_STATE_POINTERS = CMD_MEDIA_STATE */
}
-static void gen75_vme_curbe_load(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_vme_curbe_load(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, 4);
OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | 2);
ADVANCE_BATCH(batch);
}
-static void gen75_vme_idrt(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
+static void gen75_vme_idrt(VADriverContextP ctx,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, 4);
OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | 2);
}
static int gen75_vme_media_object(VADriverContextP ctx,
- struct encode_state *encode_state,
- int mb_x, int mb_y,
- int kernel, unsigned int mb_intra_ub,
- struct gen6_encoder_context *gen6_encoder_context)
+ struct encode_state *encode_state,
+ int mb_x, int mb_y,
+ int kernel, unsigned int mb_intra_ub,
+ struct gen6_encoder_context *gen6_encoder_context,
+ struct intel_batchbuffer *batch)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
- struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
int mb_width = ALIGN(obj_surface->orig_width, 16) / 16;
int len_in_dowrds = 8;
+ if (batch == NULL)
+ batch = gen6_encoder_context->base.batch;
+
BEGIN_BATCH(batch, len_in_dowrds);
OUT_BATCH(batch, CMD_MEDIA_OBJECT | (len_in_dowrds - 2));
intel_batchbuffer_emit_mi_flush(batch);
/*Step2: State command PIPELINE_SELECT*/
- gen75_vme_pipeline_select(ctx, gen6_encoder_context);
+ gen75_vme_pipeline_select(ctx, gen6_encoder_context, batch);
/*Step3: State commands configuring pipeline states*/
- gen75_vme_state_base_address(ctx, gen6_encoder_context);
- gen75_vme_vfe_state(ctx, gen6_encoder_context);
- gen75_vme_curbe_load(ctx, gen6_encoder_context);
- gen75_vme_idrt(ctx, gen6_encoder_context);
+ gen75_vme_state_base_address(ctx, gen6_encoder_context, batch);
+ gen75_vme_vfe_state(ctx, gen6_encoder_context, batch);
+ gen75_vme_curbe_load(ctx, gen6_encoder_context, batch);
+ gen75_vme_idrt(ctx, gen6_encoder_context, batch);
emit_new_state = 0;
}
/*Step4: Primitive commands*/
- object_len_in_bytes = gen75_vme_media_object(ctx, encode_state, x, y, is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER, mb_intra_ub, gen6_encoder_context);
+ object_len_in_bytes = gen75_vme_media_object(ctx, encode_state, x, y, is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER, mb_intra_ub, gen6_encoder_context, batch);
if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
assert(0);
projects / platform / upstream / libva-intel-driver.git / commitdiff