di: change clkb frq from 500 to 667 for tl1 [1/1]

PD#SWPL-6762

Problem:
di clkb frq is not right

Solution:
change from 500 to 667

Verify:
tl1

Change-Id: I9242fec37f7527203d1d00cbcdfb79c4f09e9595
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
index 8824a55..b260242 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
@@ -210,9 +210,11 @@
                                0 40 1>;
                interrupt-names = "pre_irq", "post_irq";
                clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
-                       <&clkc CLKID_VPU_CLKB_COMP>;
+                       <&clkc CLKID_VPU_CLKB_COMP>,
+                       <&clkc CLKID_VPU_MUX>;
                clock-names = "vpu_clkb_tmp_composite",
-                       "vpu_clkb_composite";
+                       "vpu_clkb_composite",
+                       "vpu_mux";
                clock-range = <334 667>;
                /* buffer-size = <3621952>;(yuv422 8bit) */
                buffer-size = <4074560>;/*yuv422 fullpack*/

diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c
index d2850cf..bcd8242 100644 (file)
--- a/drivers/amlogic/media/deinterlace/deinterlace.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace.c
@@ -129,7 +129,7 @@ static di_dev_t *de_devp;
 static dev_t di_devno;
 static struct class *di_clsp;
 
-static const char version_s[] = "2019-0422b:vscale_skip v is odd";
+static const char version_s[] = "2019-04-12b:chg clkb from 500 to 667 for tl1";
 
 static int bypass_state = 1;
 static int bypass_all;
@@ -7782,6 +7782,7 @@ static void di_get_vpu_clkb(struct device *dev, struct di_dev_s *pdev)
        int ret = 0;
        unsigned int tmp_clk[2] = {0, 0};
        struct clk *vpu_clk = NULL;
+       struct clk *clkb_tmp_comp = NULL;
 
        vpu_clk = clk_get(dev, "vpu_mux");
        if (IS_ERR(vpu_clk))
@@ -7802,9 +7803,22 @@ static void di_get_vpu_clkb(struct device *dev, struct di_dev_s *pdev)
                pdev->clkb_max_rate);
        #ifdef CLK_TREE_SUPPORT
        pdev->vpu_clkb = clk_get(dev, "vpu_clkb_composite");
+       if (is_meson_tl1_cpu()) {
+               clkb_tmp_comp = clk_get(dev, "vpu_clkb_tmp_composite");
+               if (IS_ERR(clkb_tmp_comp))
+                       pr_err("clkb_tmp_comp error\n");
+               else {
+                       if (!IS_ERR(vpu_clk))
+                               clk_set_parent(clkb_tmp_comp, vpu_clk);
+               }
+       }
+
        if (IS_ERR(pdev->vpu_clkb))
                pr_err("%s: get vpu clkb gate error.\n", __func__);
-       clk_set_rate(pdev->vpu_clkb, pdev->clkb_min_rate);
+       else {
+               clk_set_rate(pdev->vpu_clkb, pdev->clkb_min_rate);
+               pr_info("get clkb rate:%ld\n", clk_get_rate(pdev->vpu_clkb));
+       }
        #endif
 }