drm/bridge: anx7625: Fix Set HPD irq detect window to 2ms

[ Upstream commit e3af7053de3f685c96158373bc234b2feca1f160 ]

Polling firmware HPD GPIO status, set HPD irq detect window to 2ms
after firmware HPD GPIO initial done

Signed-off-by: Xin Ji <xji@analogixsemi.com>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20231120091038.284825-2-xji@analogixsemi.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 5168628..29d9149 100644 (file)
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1298,10 +1298,32 @@ static void anx7625_config(struct anx7625_data *ctx)
                          XTAL_FRQ_SEL, XTAL_FRQ_27M);
 }
 
+static int anx7625_hpd_timer_config(struct anx7625_data *ctx)
+{
+       int ret;
+
+       /* Set irq detect window to 2ms */
+       ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
+                               HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF);
+       ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
+                                HPD_DET_TIMER_BIT8_15,
+                                (HPD_TIME >> 8) & 0xFF);
+       ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
+                                HPD_DET_TIMER_BIT16_23,
+                                (HPD_TIME >> 16) & 0xFF);
+
+       return ret;
+}
+
+static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx)
+{
+       return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, GPIO_CTRL_2);
+}
+
 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
 {
        struct device *dev = ctx->dev;
-       int ret;
+       int ret, val;
 
        /* Reset main ocm */
        ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
@@ -1315,6 +1337,19 @@ static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
                DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n");
        else
                DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n");
+
+       /*
+        * Make sure the HPD GPIO already be configured after OCM release before
+        * setting HPD detect window register. Here we poll the status register
+        * at maximum 40ms, then config HPD irq detect window register
+        */
+       readx_poll_timeout(anx7625_read_hpd_gpio_config_status,
+                          ctx, val,
+                          ((val & HPD_SOURCE) || (val < 0)),
+                          2000, 2000 * 20);
+
+       /* Set HPD irq detect window to 2ms */
+       anx7625_hpd_timer_config(ctx);
 }
 
 static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
@@ -1437,20 +1472,6 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx)
 
 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
 {
-       int ret;
-
-       /* Set irq detect window to 2ms */
-       ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
-                               HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF);
-       ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
-                                HPD_DET_TIMER_BIT8_15,
-                                (HPD_TIME >> 8) & 0xFF);
-       ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
-                                HPD_DET_TIMER_BIT16_23,
-                                (HPD_TIME >> 16) & 0xFF);
-       if (ret < 0)
-               return ret;
-
        return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
 }
 

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
index 80d3fb4..39ed35d 100644 (file)
--- a/drivers/gpu/drm/bridge/analogix/anx7625.h
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
@@ -259,6 +259,10 @@
 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in  0: no RX in */
 #define AP_DISABLE_PD BIT(6)
 #define AP_DISABLE_DISPLAY BIT(7)
+
+#define GPIO_CTRL_2   0x49
+#define HPD_SOURCE    BIT(6)
+
 /***************************************************************/
 /* Register definition of device address 0x84 */
 #define  MIPI_PHY_CONTROL_3            0x03