mfld-pmu: [REVERT ME] Do not put SRAM in D0i3 during S0i3/S0i1/S3 on CVT Platform.

BZ: 25898

Putting SRAM (lss 12, lss 13) into D0ix caused SRAM Error (F504) on CVT Platform.
So keep it in D0 state untill issue is resolved.
This Work around we are tracking through  BZ 28764.

Change-Id: I029800fd8841cc9abd635c7405fa60dd3deec240
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Reviewed-on: http://android.intel.com:8080/40521
Reviewed-by: Mansoor, Illyas <illyas.mansoor@intel.com>
Reviewed-by: Gross, Mark <mark.gross@intel.com>
Reviewed-by: Cuesta, FernandX <fernandx.cuesta@intel.com>
Tested-by: Cuesta, FernandX <fernandx.cuesta@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/arch/x86/platform/intel-mid/mfld-pmu.h b/arch/x86/platform/intel-mid/mfld-pmu.h
index 7f95626..40fd39f 100644 (file)
--- a/arch/x86/platform/intel-mid/mfld-pmu.h
+++ b/arch/x86/platform/intel-mid/mfld-pmu.h
@@ -412,6 +412,21 @@
 #define IGNORE_S3_WKC0 SSWKC(PMU_AONT_LSS_02)
 #define IGNORE_S3_WKC1 SSWKC(PMU_ADC_LSS_42-32)
 
+#ifdef CONFIG_BOARD_CTP
+/* FIXME:: CVT Platform gives SRAM Error if SRAM(lss12, 13) is put in D0i3 */
+#define S0I3_SSS0 ( \
+       SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
+       SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
+       SSMSK(D0I3_MASK, PMU_AONT_LSS_02) | \
+       SSMSK(D0I3_MASK, PMU_HSI_LSS_03) | \
+       SSMSK(D0I2_MASK, PMU_SECURITY_LSS_04) | \
+       SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
+       SSMSK(D0I1_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I1_MASK, PMU_USB_HSIC_LSS_07) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_ENGINE_LSS_08) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_DMA_LSS_09) | \
+       SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+#else
 #define S0I3_SSS0 ( \
        SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
        SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
@@ -426,6 +441,8 @@
        SSMSK(D0I3_MASK, PMU_SRAM_LSS_12) | \
        SSMSK(D0I3_MASK, PMU_SRAM_LSS_13) | \
        SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+#endif
+
 
 #define S0I3_SSS1 ( \
        SSMSK(D0I3_MASK, PMU_SPI1_LSS_18-16) | \