memory: renesas-rpc-if: Add support for R-Car Gen4

The SPI Multi I/O Bus Controller (RPC-IF) on R-Car Gen4 SoCs is very
similar to the RPC-IF on R-Car Gen3 SoCs.  It does support four instead
of three bits of strobe timing adjustment (STRTIM), and thus requires a
new mask and new settings.

Inspired by a patch in the BSP by Cong Dang.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/4d0824bf5ed0fb95c51cd36f9a3f0f562b1a6bf8.1665583089.git.geert+renesas@glider.be
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 61c288d403750b14046a1d96fd7d508a22c5132b..09cd4318a83d84d3d97e90ad60287fc6d5d3e1a3 100644 (file)
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -136,7 +136,8 @@
 #define RPCIF_PHYCNT_DDRCAL    BIT(19)
 #define RPCIF_PHYCNT_HS                BIT(18)
 #define RPCIF_PHYCNT_CKSEL(v)  (((v) & 0x3) << 16) /* valid only for RZ/G2L */
-#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */
+#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
+
 #define RPCIF_PHYCNT_WBUF2     BIT(4)
 #define RPCIF_PHYCNT_WBUF      BIT(2)
 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
@@ -323,6 +324,9 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
        if (rpc->type == RPCIF_RCAR_GEN3)
                regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
                                   RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
+       else if (rpc->type == RPCIF_RCAR_GEN4)
+               regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
+                                  RPCIF_PHYCNT_STRTIM(15), RPCIF_PHYCNT_STRTIM(15));
 
        regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
                           RPCIF_PHYOFFSET1_DDRTMG(3));
@@ -333,17 +337,17 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
                regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
                                   RPCIF_PHYINT_WPVAL, 0);
 
-       if (rpc->type == RPCIF_RCAR_GEN3)
-               regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
-                                  RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
-                                  RPCIF_CMNCR_MOIIO(3) |
-                                  RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
-       else
+       if (rpc->type == RPCIF_RZ_G2L)
                regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
                                   RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
                                   RPCIF_CMNCR_BSZ(3),
                                   RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
                                   RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
+       else
+               regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
+                                  RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
+                                  RPCIF_CMNCR_MOIIO(3) |
+                                  RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 
        /* Set RCF after BSZ update */
        regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
@@ -718,6 +722,7 @@ static int rpcif_remove(struct platform_device *pdev)
 
 static const struct of_device_id rpcif_of_match[] = {
        { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
+       { .compatible = "renesas,rcar-gen4-rpc-if", .data = (void *)RPCIF_RCAR_GEN4 },
        { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
        {},
 };

diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h
index 9c0ad64b8d292d49746c542e0c1b6bb261475e32..862eff613dc7963d112f98e2a5ce6bc48bfd2b7d 100644 (file)
--- a/include/memory/renesas-rpc-if.h
+++ b/include/memory/renesas-rpc-if.h
@@ -59,6 +59,7 @@ struct rpcif_op {
 
 enum rpcif_type {
        RPCIF_RCAR_GEN3,
+       RPCIF_RCAR_GEN4,
        RPCIF_RZ_G2L,
 };