The "DMA Config" registers are sequential in the enum ni_gpct_register.
Replace this inline CamelCase function with a simple define.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
counter_index));
}
ni_tio_set_bits(counter,
- NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0,
+ NITIO_DMA_CFG_REG(counter->counter_index), ~0,
0x0);
ni_tio_set_bits(counter,
NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
#define NITIO_RESET_REG(x) (NITIO_G01_RESET + ((x) / 2))
#define NITIO_STATUS1_REG(x) (NITIO_G01_STATUS1 + ((x) / 2))
#define NITIO_STATUS2_REG(x) (NITIO_G01_STATUS2 + ((x) / 2))
-
-static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(unsigned idx)
-{
- switch (idx) {
- case 0:
- return NITIO_G0_DMA_CFG;
- case 1:
- return NITIO_G1_DMA_CFG;
- case 2:
- return NITIO_G2_DMA_CFG;
- case 3:
- return NITIO_G3_DMA_CFG;
- }
- return 0;
-}
+#define NITIO_DMA_CFG_REG(x) (NITIO_G0_DMA_CFG + (x))
static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(unsigned idx)
{
if (read_not_write == 0)
gi_dma_config_bits |= Gi_DMA_Write_Bit;
ni_tio_set_bits(counter,
- NITIO_Gi_DMA_Config_Reg(counter->
+ NITIO_DMA_CFG_REG(counter->
counter_index),
Gi_DMA_Enable_Bit | Gi_DMA_Int_Bit |
Gi_DMA_Write_Bit, gi_dma_config_bits);