Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-next...

Allwinner sunXi SoCs clock changes

Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.

Conflicts:
	drivers/clk/sunxi/clk-sunxi.c

diff --combined drivers/clk/sunxi/clk-sunxi.c
index 9bbd035145409b9908ca25fecfd412d5e7345840,9665cb8d023878231c0fa5beeffe198c3ba4f5cc..98fec4e4baa76ed5a0077ae57834da8e47c80626
--- 1/drivers/clk/sunxi/clk-sunxi.c
--- 2/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@@ -16,6 -16,7 +16,6 @@@
  
  #include <linux/clk-provider.h>
  #include <linux/clkdev.h>
 -#include <linux/clk/sunxi.h>
  #include <linux/of.h>
  #include <linux/of_address.h>
  
@@@ -37,18 -38,16 +37,16 @@@ static void __init sun4i_osc_clk_setup(
        const char *clk_name = node->name;
        u32 rate;
  
+       if (of_property_read_u32(node, "clock-frequency", &rate))
+               return;
+ 
        /* allocate fixed-rate and gate clock structs */
        fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
        if (!fixed)
                return;
        gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-       if (!gate) {
-               kfree(fixed);
-               return;
-       }
- 
-       if (of_property_read_u32(node, "clock-frequency", &rate))
-               return;
+       if (!gate)
+               goto err_free_fixed;
  
        /* set up gate and fixed rate properties */
        gate->reg = of_iomap(node, 0);
@@@ -63,10 -62,18 +61,18 @@@
                        &gate->hw, &clk_gate_ops,
                        CLK_IS_ROOT);
  
-       if (!IS_ERR(clk)) {
-               of_clk_add_provider(node, of_clk_src_simple_get, clk);
-               clk_register_clkdev(clk, clk_name, NULL);
-       }
+       if (IS_ERR(clk))
+               goto err_free_gate;
+ 
+       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       clk_register_clkdev(clk, clk_name, NULL);
+ 
+       return;
+ 
+ err_free_gate:
+       kfree(gate);
+ err_free_fixed:
+       kfree(fixed);
  }
  CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
  
@@@ -616,8 -623,36 +622,33 @@@ static void __init of_sunxi_table_clock
        }
  }
  
- static void __init sunxi_init_clocks(struct device_node *np)
+ /**
+  * System clock protection
+  *
+  * By enabling these critical clocks, we prevent their accidental gating
+  * by the framework
+  */
+ static void __init sunxi_clock_protect(void)
+ {
+       struct clk *clk;
+ 
+       /* memory bus clock - sun5i+ */
+       clk = clk_get(NULL, "mbus");
+       if (!IS_ERR(clk)) {
+               clk_prepare_enable(clk);
+               clk_put(clk);
+       }
+ 
+       /* DDR clock - sun4i+ */
+       clk = clk_get(NULL, "pll5_ddr");
+       if (!IS_ERR(clk)) {
+               clk_prepare_enable(clk);
+               clk_put(clk);
+       }
+ }
+ 
 -void __init sunxi_init_clocks(void)
++static void __init sunxi_init_clocks(void)
  {
 -      /* Register all the simple and basic clocks on DT */
 -      of_clk_init(NULL);
 -
        /* Register factor clocks */
        of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
  
@@@ -629,9 -664,7 +660,12 @@@
  
        /* Register gate clocks */
        of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
+ 
+       /* Enable core system clocks */
+       sunxi_clock_protect();
  }
 +CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);