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dt-bindings: display: Fix spacing in lvds.yaml
authorMarek Vasut <marex@denx.de>
Mon, 17 May 2021 22:43:36 +0000 (00:43 +0200)
committerRob Herring <robh@kernel.org>
Thu, 20 May 2021 20:21:19 +0000 (15:21 -0500)
Add missing spaces to make the diagrams readable, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: devicetree@vger.kernel.org
To: dri-devel@lists.freedesktop.org
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20210517224336.409301-1-marex@denx.de
Signed-off-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/display/panel/lvds.yaml patch | blob | history

diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml
index 3116460..49460c9 100644 (file)
--- a/Documentation/devicetree/bindings/display/panel/lvds.yaml
+++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml
@@ -51,37 +51,37 @@ properties:
       - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
         [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
 
-      Slot         0       1       2       3       4       5       6
-            ________________                         _________________
-      Clock                    \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
-      DATA0    ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
-      DATA1    ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
-      DATA2    ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
+      Slot          0       1       2       3       4       5       6
+                ________________                         _________________
+      Clock                     \_______________________/
+                  ______  ______  ______  ______  ______  ______  ______
+      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
+      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
+      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
 
       - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
         specifications. Data are transferred as follows on 4 LVDS lanes.
 
-      Slot         0       1       2       3       4       5       6
-            ________________                         _________________
-      Clock                    \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
-      DATA0    ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
-      DATA1    ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
-      DATA2    ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
-      DATA3    ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
+      Slot          0       1       2       3       4       5       6
+                ________________                         _________________
+      Clock                     \_______________________/
+                  ______  ______  ______  ______  ______  ______  ______
+      DATA0     ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
+      DATA1     ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
+      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
+      DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
 
       - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
         Data are transferred as follows on 4 LVDS lanes.
 
-      Slot         0       1       2       3       4       5       6
-            ________________                         _________________
-      Clock                    \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
-      DATA0    ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
-      DATA1    ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
-      DATA2    ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
-      DATA3    ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
+      Slot          0       1       2       3       4       5       6
+                ________________                         _________________
+      Clock                     \_______________________/
+                  ______  ______  ______  ______  ______  ______  ______
+      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
+      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
+      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
+      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
 
       Control signals are mapped as follows.
 
Domain: System / Kernel;