ASoC: dwc: Add DMACR handling

Add control of the DMACR register, which is required for paced DMA
(i.e. DREQ) support.

Signed-off-by: Phil Elwell <phil@raspberrypi.com>

diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c
index dacb160..bdc8bfa 100644 (file)
--- a/sound/soc/dwc/dwc-i2s.c
+++ b/sound/soc/dwc/dwc-i2s.c
@@ -248,7 +248,7 @@ static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
 {
        u32 ch_reg;
        struct i2s_clk_config_data *config = &dev->config;
-
+       u32 dmacr = 0;
 
        i2s_disable_channels(dev, stream);
 
@@ -260,6 +260,7 @@ static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
                                      dev->fifo_th - 1);
                        i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |
                                      dev->tdm_mask << TER_TXSLOT_SHIFT);
+                       dmacr |= (DMACR_DMAEN_TXCH0 << ch_reg);
                } else {
                        i2s_write_reg(dev->i2s_base, RCR(ch_reg),
                                      dev->xfer_resolution);
@@ -267,9 +268,15 @@ static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
                                      dev->fifo_th - 1);
                        i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |
                                      dev->tdm_mask << RER_RXSLOT_SHIFT);
+                       dmacr |= (DMACR_DMAEN_RXCH0 << ch_reg);
                }
-
        }
+       if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+               dmacr |= DMACR_DMAEN_TX;
+       else if (stream == SNDRV_PCM_STREAM_CAPTURE)
+               dmacr |= DMACR_DMAEN_RX;
+
+       i2s_write_reg(dev->i2s_base, I2S_DMACR, dmacr);
 }
 
 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,

diff --git a/sound/soc/dwc/local.h b/sound/soc/dwc/local.h
index dce88c9..6b08979 100644 (file)
--- a/sound/soc/dwc/local.h
+++ b/sound/soc/dwc/local.h
@@ -63,6 +63,17 @@
 #define TER_TXSLOT_SHIFT       8
 #define TER_TXCHEN     BIT(0)
 
+#define DMACR_DMAEN_TX         BIT(17)
+#define DMACR_DMAEN_RX         BIT(16)
+#define DMACR_DMAEN_TXCH3      BIT(11)
+#define DMACR_DMAEN_TXCH2      BIT(10)
+#define DMACR_DMAEN_TXCH1      BIT(9)
+#define DMACR_DMAEN_TXCH0      BIT(8)
+#define DMACR_DMAEN_RXCH3      BIT(3)
+#define DMACR_DMAEN_RXCH2      BIT(2)
+#define DMACR_DMAEN_RXCH1      BIT(1)
+#define DMACR_DMAEN_RXCH0      BIT(0)
+
 /* I2SCOMPRegisters */
 #define I2S_COMP_PARAM_2       0x01F0
 #define I2S_COMP_PARAM_1       0x01F4