[cgen]

	* cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder.
	(mep_config_map): Regenerate.

	* cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as
	ivc2-specific names.
	(simm8p20): New.
	(cmovc): move to after field definitions, use ivc2-specific
	register names.
	(cpmovi_b_P0S_P1): New.

[utils/mep]

	* mepcfgtool.c (do_cgen_config_opc): Propagate endianness and VLIW
	size to default configuration.

[sid/component/cgen-cpu/mep]

	* mep-cop1-16-decode.cxx: Regenerate.
	* mep-cop1-16-decode.h: Regenerate.
	* mep-cop1-16-model.cxx: Regenerate.
	* mep-cop1-16-model.h: Regenerate.
	* mep-cop1-16-sem.cxx: Regenerate.
	* mep-cop1-64-decode.cxx: Regenerate.
	* mep-cop1-64-decode.h: Regenerate.
	* mep-cop1-64-model.cxx: Regenerate.
	* mep-cop1-64-model.h: Regenerate.
	* mep-cop1-64-sem.cxx: Regenerate.

[opcodes]

	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.
	* mep-opc.h: Regenerate.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 634ca03..d0b5d8e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2009-05-22  DJ Delorie  <dj@redhat.com>
+
+       * mep-asm.c: Regenerate.
+       * mep-desc.c: Regenerate.
+       * mep-desc.h: Regenerate.
+       * mep-dis.c: Regenerate.
+       * mep-ibld.c: Regenerate.
+       * mep-opc.c: Regenerate.
+       * mep-opc.h: Regenerate.
+
 2009-05-22  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 
        * i386-opc.h (Cpusse5): Delete.

diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 4f92cbd..1feff81 100644 (file)
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -980,8 +980,11 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_IVC_X_6_3 :
       errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_3, (unsigned long *) (& fields->f_ivc2_3u6));
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ccrn);
+      break;
     case MEP_OPERAND_IVC2CCRN :
-      errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_ivc2_ccrn);
+      errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ivc2_ccrn);
       break;
     case MEP_OPERAND_IVC2CRN :
       errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_crnx);
@@ -1112,6 +1115,9 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_SIMM8P0 :
       errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P0, (long *) (& fields->f_ivc2_8s0));
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P20, (long *) (& fields->f_ivc2_8s20));
+      break;
     case MEP_OPERAND_SIMM8P4 :
       errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P4, (long *) (& fields->f_ivc2_8s4));
       break;

diff --git a/opcodes/mep-desc.c b/opcodes/mep-desc.c
index dc64c7a..d8a1988 100644 (file)
--- a/opcodes/mep-desc.c
+++ b/opcodes/mep-desc.c
@@ -466,40 +466,67 @@ CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2 =
 
 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_ivc2_entries[] =
 {
-  { "$ivc2_acc0_0", 16, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc0_1", 17, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc0_2", 18, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc0_3", 19, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc0_4", 20, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc0_5", 21, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc0_6", 22, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc0_7", 23, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_0", 24, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_1", 25, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_2", 26, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_3", 27, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_4", 28, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_5", 29, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_6", 30, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_acc1_7", 31, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_csar0", 0, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_csar1", 15, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_cc", 1, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_cofr0", 4, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_cofr1", 5, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_cofa0", 6, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_cofa1", 7, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
-  { "$ivc2_ccr14", 14, {0, {{{0, 0}}}}, 0, 0 }
+  { "$csar0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "$cc", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "$cofr0", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "$cofr1", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "$cofa0", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "$cofa1", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "$csar1", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc00", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc01", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc02", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc03", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc04", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc05", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc06", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc07", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc10", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc11", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc12", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc13", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc14", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc15", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc16", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "$acc17", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2 =
 {
   & mep_cgen_opval_h_ccr_ivc2_entries[0],
-  28,
+  55,
   0, 0, 0, 0, ""
 };
 
@@ -1262,6 +1289,10 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
   { "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } }, 
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
+/* simm8p20: sImm8p20 */
+  { "simm8p20", MEP_OPERAND_SIMM8P20, HW_H_SINT, 20, 8,
+    { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 /* imm8p20: Imm8p20 */
   { "imm8p20", MEP_OPERAND_IMM8P20, HW_H_UINT, 20, 8,
     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } }, 
@@ -1311,9 +1342,13 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
     { 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } }, 
     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 /* ivc2ccrn: copro control reg CCRn */
-  { "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR, 0, 6,
+  { "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR_IVC2, 0, 6,
     { 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } }, 
     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
+/* ivc2c3ccrn: copro control reg CCRn */
+  { "ivc2c3ccrn", MEP_OPERAND_IVC2C3CCRN, HW_H_CCR_IVC2, 4, 6,
+    { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
@@ -2473,12 +2508,12 @@ static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
     MEP_INSN_CMOV_RN_CRM, "cmov-rn-crm", "cmov", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
   },
-/* cmovc $ccrn,$rm */
+/* cmovc $ivc2c3ccrn,$rm */
   {
     MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
   },
-/* cmovc $rm,$ccrn */
+/* cmovc $rm,$ivc2c3ccrn */
   {
     MEP_INSN_CMOVC_RN_CCRM, "cmovc-rn-ccrm", "cmovc", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
@@ -5253,6 +5288,11 @@ static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
     MEP_INSN_C1NOP_P1, "c1nop_P1", "c1nop", 32,
     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
   },
+/* cpmovi.b $crqp,$simm8p20 */
+  {
+    MEP_INSN_CPMOVI_B_P0S_P1, "cpmovi_b_P0S_P1", "cpmovi.b", 32,
+    { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+  },
 /* cpadda1u.b $crqp,$crpp */
   {
     MEP_INSN_CPADDA1U_B_P1, "cpadda1u_b_P1", "cpadda1u.b", 32,

diff --git a/opcodes/mep-desc.h b/opcodes/mep-desc.h
index 19832e0..890227c 100644 (file)
--- a/opcodes/mep-desc.h
+++ b/opcodes/mep-desc.h
@@ -263,15 +263,15 @@ typedef enum cgen_operand_type {
  , MEP_OPERAND_IMM5P7, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4
  , MEP_OPERAND_IMM3P5, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10
  , MEP_OPERAND_IMM5P8, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23
- , MEP_OPERAND_IMM3P25, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_IMM8P20
- , MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2
- , MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0
- , MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN
- , MEP_OPERAND_MAX
+ , MEP_OPERAND_IMM3P25, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20
+ , MEP_OPERAND_IMM8P20, MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP
+ , MEP_OPERAND_IVC_X_0_2, MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5
+ , MEP_OPERAND_IMM16P0, MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN
+ , MEP_OPERAND_IVC2CCRN, MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 120
+#define MAX_OPERANDS 122
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 8

diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index ee0d507..c1f3be3 100644 (file)
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -558,7 +558,7 @@ mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_
   else
     e = 0;
 
-  if ((buf[0^e] & 0xf0) != 0xf0)
+  if (((unsigned char)buf[0^e] & 0xf0) < 0xc0)
     {
       /*      <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
       /* V1   [-----core-----][--------p0s-------][------------p1------------] */
@@ -928,8 +928,11 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_IVC_X_6_3 :
       print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
     case MEP_OPERAND_IVC2CCRN :
-      print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
       break;
     case MEP_OPERAND_IVC2CRN :
       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
@@ -1060,6 +1063,9 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_SIMM8P0 :
       print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      print_normal (cd, info, fields->f_ivc2_8s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
     case MEP_OPERAND_SIMM8P4 :
       print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;

diff --git a/opcodes/mep-ibld.c b/opcodes/mep-ibld.c
index 69fedea..bca4005 100644 (file)
--- a/opcodes/mep-ibld.c
+++ b/opcodes/mep-ibld.c
@@ -878,6 +878,20 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_IVC_X_6_3 :
       errmsg = insert_normal (cd, fields->f_ivc2_3u6, 0, 0, 6, 3, 32, total_length, buffer);
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      {
+{
+  FLD (f_ccrn_hi) = ((((unsigned int) (FLD (f_ccrn)) >> (4))) & (3));
+  FLD (f_ccrn_lo) = ((FLD (f_ccrn)) & (15));
+}
+        errmsg = insert_normal (cd, fields->f_ccrn_hi, 0, 0, 28, 2, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_ccrn_lo, 0, 0, 4, 4, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
     case MEP_OPERAND_IVC2CCRN :
       {
 {
@@ -1066,6 +1080,9 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_SIMM8P0 :
       errmsg = insert_normal (cd, fields->f_ivc2_8s0, 0|(1<<CGEN_IFLD_SIGNED), 0, 0, 8, 32, total_length, buffer);
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      errmsg = insert_normal (cd, fields->f_ivc2_8s20, 0|(1<<CGEN_IFLD_SIGNED), 0, 20, 8, 32, total_length, buffer);
+      break;
     case MEP_OPERAND_SIMM8P4 :
       errmsg = insert_normal (cd, fields->f_ivc2_8s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 32, total_length, buffer);
       break;
@@ -1442,6 +1459,15 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_IVC_X_6_3 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 3, 32, total_length, pc, & fields->f_ivc2_3u6);
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ccrn_hi);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ccrn_lo);
+        if (length <= 0) break;
+  FLD (f_ccrn) = ((((FLD (f_ccrn_hi)) << (4))) | (FLD (f_ccrn_lo)));
+      }
+      break;
     case MEP_OPERAND_IVC2CCRN :
       {
         length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_h2);
@@ -1609,6 +1635,9 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_SIMM8P0 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8s0);
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8s20);
+      break;
     case MEP_OPERAND_SIMM8P4 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 32, total_length, pc, & fields->f_ivc2_8s4);
       break;
@@ -1888,6 +1917,9 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       value = fields->f_ivc2_3u6;
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      value = fields->f_ccrn;
+      break;
     case MEP_OPERAND_IVC2CCRN :
       value = fields->f_ivc2_ccrn;
       break;
@@ -2020,6 +2052,9 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_SIMM8P0 :
       value = fields->f_ivc2_8s0;
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      value = fields->f_ivc2_8s20;
+      break;
     case MEP_OPERAND_SIMM8P4 :
       value = fields->f_ivc2_8s4;
       break;
@@ -2265,6 +2300,9 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       value = fields->f_ivc2_3u6;
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      value = fields->f_ccrn;
+      break;
     case MEP_OPERAND_IVC2CCRN :
       value = fields->f_ivc2_ccrn;
       break;
@@ -2397,6 +2435,9 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_SIMM8P0 :
       value = fields->f_ivc2_8s0;
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      value = fields->f_ivc2_8s20;
+      break;
     case MEP_OPERAND_SIMM8P4 :
       value = fields->f_ivc2_8s4;
       break;
@@ -2643,6 +2684,9 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       fields->f_ivc2_3u6 = value;
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      fields->f_ccrn = value;
+      break;
     case MEP_OPERAND_IVC2CCRN :
       fields->f_ivc2_ccrn = value;
       break;
@@ -2763,6 +2807,9 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_SIMM8P0 :
       fields->f_ivc2_8s0 = value;
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      fields->f_ivc2_8s20 = value;
+      break;
     case MEP_OPERAND_SIMM8P4 :
       fields->f_ivc2_8s4 = value;
       break;
@@ -2994,6 +3041,9 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       fields->f_ivc2_3u6 = value;
       break;
+    case MEP_OPERAND_IVC2C3CCRN :
+      fields->f_ccrn = value;
+      break;
     case MEP_OPERAND_IVC2CCRN :
       fields->f_ivc2_ccrn = value;
       break;
@@ -3114,6 +3164,9 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_SIMM8P0 :
       fields->f_ivc2_8s0 = value;
       break;
+    case MEP_OPERAND_SIMM8P20 :
+      fields->f_ivc2_8s20 = value;
+      break;
     case MEP_OPERAND_SIMM8P4 :
       fields->f_ivc2_8s4 = value;
       break;

diff --git a/opcodes/mep-opc.c b/opcodes/mep-opc.c
index 7bf92b6..1a8321e 100644 (file)
--- a/opcodes/mep-opc.c
+++ b/opcodes/mep-opc.c
@@ -92,7 +92,7 @@ mep_config_map_struct mep_config_map[] =
 {
   /* config-map-start */
   /* Default entry: first module, with all options enabled. */
-  { "", 0,  EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,1, 0, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) },
+  { "", 0,  EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) },
   { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" },
          0
        | (1 << CGEN_INSN_OPTIONAL_CP_INSN)
@@ -558,6 +558,10 @@ static const CGEN_IFMT ifmt_cpmoviu_w_P0_P1 ATTRIBUTE_UNUSED = {
   32, 32, 0xf8300f, { { F (F_IVC2_IMM16P0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_4U28) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_cpmovi_b_P0S_P1 ATTRIBUTE_UNUSED = {
+  32, 32, 0xfff8300f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_8U20) }, { F (F_IVC2_4U28) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_cpfmulia1s0u_b_P1 ATTRIBUTE_UNUSED = {
   32, 32, 0xf801ff, { { F (F_IVC2_8S0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } }
 };
@@ -1951,16 +1955,16 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (RM), ',', OP (CRNX64), 0 } },
     & ifmt_cmov_crn_rm, { 0xf007f001 }
   },
-/* cmovc $ccrn,$rm */
+/* cmovc $ivc2c3ccrn,$rm */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (CCRN), ',', OP (RM), 0 } },
+    { { MNEM, ' ', OP (IVC2C3CCRN), ',', OP (RM), 0 } },
     & ifmt_cmovc_ccrn_rm, { 0xf007f002 }
   },
-/* cmovc $rm,$ccrn */
+/* cmovc $rm,$ivc2c3ccrn */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RM), ',', OP (CCRN), 0 } },
+    { { MNEM, ' ', OP (RM), ',', OP (IVC2C3CCRN), 0 } },
     & ifmt_cmovc_ccrn_rm, { 0xf007f003 }
   },
 /* cmovh $crnx64,$rm */
@@ -5287,6 +5291,12 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, 0 } },
     & ifmt_c0nop_P0_P0S, { 0x0 }
   },
+/* cpmovi.b $crqp,$simm8p20 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (CRQP), ',', OP (SIMM8P20), 0 } },
+    & ifmt_cpmovi_b_P0S_P1, { 0xb00000 }
+  },
 /* cpadda1u.b $crqp,$crpp */
   {
     { 0, 0, 0, 0 },

diff --git a/opcodes/mep-opc.h b/opcodes/mep-opc.h
index f83d84f..0704c30 100644 (file)
--- a/opcodes/mep-opc.h
+++ b/opcodes/mep-opc.h
@@ -296,39 +296,39 @@ typedef enum cgen_insn_type {
  , MEP_INSN_CPSLAI3_H_P0_P1, MEP_INSN_CPSLAI3_W_P0_P1, MEP_INSN_CPCLIPIU3_W_P0_P1, MEP_INSN_CPCLIPI3_W_P0_P1
  , MEP_INSN_CDCLIPIU3_P0_P1, MEP_INSN_CDCLIPI3_P0_P1, MEP_INSN_CPMOVI_H_P0_P1, MEP_INSN_CPMOVIU_W_P0_P1
  , MEP_INSN_CPMOVI_W_P0_P1, MEP_INSN_CDMOVIU_P0_P1, MEP_INSN_CDMOVI_P0_P1, MEP_INSN_C1NOP_P1
- , MEP_INSN_CPADDA1U_B_P1, MEP_INSN_CPADDA1_B_P1, MEP_INSN_CPADDUA1_H_P1, MEP_INSN_CPADDLA1_H_P1
- , MEP_INSN_CPADDACA1U_B_P1, MEP_INSN_CPADDACA1_B_P1, MEP_INSN_CPADDACUA1_H_P1, MEP_INSN_CPADDACLA1_H_P1
- , MEP_INSN_CPSUBA1U_B_P1, MEP_INSN_CPSUBA1_B_P1, MEP_INSN_CPSUBUA1_H_P1, MEP_INSN_CPSUBLA1_H_P1
- , MEP_INSN_CPSUBACA1U_B_P1, MEP_INSN_CPSUBACA1_B_P1, MEP_INSN_CPSUBACUA1_H_P1, MEP_INSN_CPSUBACLA1_H_P1
- , MEP_INSN_CPABSA1U_B_P1, MEP_INSN_CPABSA1_B_P1, MEP_INSN_CPABSUA1_H_P1, MEP_INSN_CPABSLA1_H_P1
- , MEP_INSN_CPSADA1U_B_P1, MEP_INSN_CPSADA1_B_P1, MEP_INSN_CPSADUA1_H_P1, MEP_INSN_CPSADLA1_H_P1
- , MEP_INSN_CPSETA1_H_P1, MEP_INSN_CPSETUA1_W_P1, MEP_INSN_CPSETLA1_W_P1, MEP_INSN_CPMOVA1_B_P1
- , MEP_INSN_CPMOVUA1_H_P1, MEP_INSN_CPMOVLA1_H_P1, MEP_INSN_CPMOVUUA1_W_P1, MEP_INSN_CPMOVULA1_W_P1
- , MEP_INSN_CPMOVLUA1_W_P1, MEP_INSN_CPMOVLLA1_W_P1, MEP_INSN_CPPACKA1U_B_P1, MEP_INSN_CPPACKA1_B_P1
- , MEP_INSN_CPPACKUA1_H_P1, MEP_INSN_CPPACKLA1_H_P1, MEP_INSN_CPPACKUA1_W_P1, MEP_INSN_CPPACKLA1_W_P1
- , MEP_INSN_CPMOVHUA1_W_P1, MEP_INSN_CPMOVHLA1_W_P1, MEP_INSN_CPACSUMA1_P1, MEP_INSN_CPACCPA1_P1
- , MEP_INSN_CPACSWP_P1, MEP_INSN_CPSRLA1_P1, MEP_INSN_CPSRAA1_P1, MEP_INSN_CPSLLA1_P1
- , MEP_INSN_CPSRLIA1_1_P1, MEP_INSN_CPSRAIA1_1_P1, MEP_INSN_CPSLLIA1_1_P1, MEP_INSN_CPFMULIA1S0U_B_P1
- , MEP_INSN_CPFMULIA1S0_B_P1, MEP_INSN_CPFMULIUA1S0_H_P1, MEP_INSN_CPFMULILA1S0_H_P1, MEP_INSN_CPFMADIA1S0U_B_P1
- , MEP_INSN_CPFMADIA1S0_B_P1, MEP_INSN_CPFMADIUA1S0_H_P1, MEP_INSN_CPFMADILA1S0_H_P1, MEP_INSN_CPFMULIA1S1U_B_P1
- , MEP_INSN_CPFMULIA1S1_B_P1, MEP_INSN_CPFMULIUA1S1_H_P1, MEP_INSN_CPFMULILA1S1_H_P1, MEP_INSN_CPFMADIA1S1U_B_P1
- , MEP_INSN_CPFMADIA1S1_B_P1, MEP_INSN_CPFMADIUA1S1_H_P1, MEP_INSN_CPFMADILA1S1_H_P1, MEP_INSN_CPAMULIA1U_B_P1
- , MEP_INSN_CPAMULIA1_B_P1, MEP_INSN_CPAMULIUA1_H_P1, MEP_INSN_CPAMULILA1_H_P1, MEP_INSN_CPAMADIA1U_B_P1
- , MEP_INSN_CPAMADIA1_B_P1, MEP_INSN_CPAMADIUA1_H_P1, MEP_INSN_CPAMADILA1_H_P1, MEP_INSN_CPFMULIA1U_B_P1
- , MEP_INSN_CPFMULIA1_B_P1, MEP_INSN_CPFMULIUA1_H_P1, MEP_INSN_CPFMULILA1_H_P1, MEP_INSN_CPFMADIA1U_B_P1
- , MEP_INSN_CPFMADIA1_B_P1, MEP_INSN_CPFMADIUA1_H_P1, MEP_INSN_CPFMADILA1_H_P1, MEP_INSN_CPSSQA1U_B_P1
- , MEP_INSN_CPSSQA1_B_P1, MEP_INSN_CPSSDA1U_B_P1, MEP_INSN_CPSSDA1_B_P1, MEP_INSN_CPMULA1U_B_P1
- , MEP_INSN_CPMULA1_B_P1, MEP_INSN_CPMULUA1_H_P1, MEP_INSN_CPMULLA1_H_P1, MEP_INSN_CPMULUA1U_W_P1
- , MEP_INSN_CPMULLA1U_W_P1, MEP_INSN_CPMULUA1_W_P1, MEP_INSN_CPMULLA1_W_P1, MEP_INSN_CPMADA1U_B_P1
- , MEP_INSN_CPMADA1_B_P1, MEP_INSN_CPMADUA1_H_P1, MEP_INSN_CPMADLA1_H_P1, MEP_INSN_CPMADUA1U_W_P1
- , MEP_INSN_CPMADLA1U_W_P1, MEP_INSN_CPMADUA1_W_P1, MEP_INSN_CPMADLA1_W_P1, MEP_INSN_CPMSBUA1_H_P1
- , MEP_INSN_CPMSBLA1_H_P1, MEP_INSN_CPMSBUA1U_W_P1, MEP_INSN_CPMSBLA1U_W_P1, MEP_INSN_CPMSBUA1_W_P1
- , MEP_INSN_CPMSBLA1_W_P1, MEP_INSN_CPSMADUA1_H_P1, MEP_INSN_CPSMADLA1_H_P1, MEP_INSN_CPSMADUA1_W_P1
- , MEP_INSN_CPSMADLA1_W_P1, MEP_INSN_CPSMSBUA1_H_P1, MEP_INSN_CPSMSBLA1_H_P1, MEP_INSN_CPSMSBUA1_W_P1
- , MEP_INSN_CPSMSBLA1_W_P1, MEP_INSN_CPMULSLUA1_H_P1, MEP_INSN_CPMULSLLA1_H_P1, MEP_INSN_CPMULSLUA1_W_P1
- , MEP_INSN_CPMULSLLA1_W_P1, MEP_INSN_CPSMADSLUA1_H_P1, MEP_INSN_CPSMADSLLA1_H_P1, MEP_INSN_CPSMADSLUA1_W_P1
- , MEP_INSN_CPSMADSLLA1_W_P1, MEP_INSN_CPSMSBSLUA1_H_P1, MEP_INSN_CPSMSBSLLA1_H_P1, MEP_INSN_CPSMSBSLUA1_W_P1
- , MEP_INSN_CPSMSBSLLA1_W_P1
+ , MEP_INSN_CPMOVI_B_P0S_P1, MEP_INSN_CPADDA1U_B_P1, MEP_INSN_CPADDA1_B_P1, MEP_INSN_CPADDUA1_H_P1
+ , MEP_INSN_CPADDLA1_H_P1, MEP_INSN_CPADDACA1U_B_P1, MEP_INSN_CPADDACA1_B_P1, MEP_INSN_CPADDACUA1_H_P1
+ , MEP_INSN_CPADDACLA1_H_P1, MEP_INSN_CPSUBA1U_B_P1, MEP_INSN_CPSUBA1_B_P1, MEP_INSN_CPSUBUA1_H_P1
+ , MEP_INSN_CPSUBLA1_H_P1, MEP_INSN_CPSUBACA1U_B_P1, MEP_INSN_CPSUBACA1_B_P1, MEP_INSN_CPSUBACUA1_H_P1
+ , MEP_INSN_CPSUBACLA1_H_P1, MEP_INSN_CPABSA1U_B_P1, MEP_INSN_CPABSA1_B_P1, MEP_INSN_CPABSUA1_H_P1
+ , MEP_INSN_CPABSLA1_H_P1, MEP_INSN_CPSADA1U_B_P1, MEP_INSN_CPSADA1_B_P1, MEP_INSN_CPSADUA1_H_P1
+ , MEP_INSN_CPSADLA1_H_P1, MEP_INSN_CPSETA1_H_P1, MEP_INSN_CPSETUA1_W_P1, MEP_INSN_CPSETLA1_W_P1
+ , MEP_INSN_CPMOVA1_B_P1, MEP_INSN_CPMOVUA1_H_P1, MEP_INSN_CPMOVLA1_H_P1, MEP_INSN_CPMOVUUA1_W_P1
+ , MEP_INSN_CPMOVULA1_W_P1, MEP_INSN_CPMOVLUA1_W_P1, MEP_INSN_CPMOVLLA1_W_P1, MEP_INSN_CPPACKA1U_B_P1
+ , MEP_INSN_CPPACKA1_B_P1, MEP_INSN_CPPACKUA1_H_P1, MEP_INSN_CPPACKLA1_H_P1, MEP_INSN_CPPACKUA1_W_P1
+ , MEP_INSN_CPPACKLA1_W_P1, MEP_INSN_CPMOVHUA1_W_P1, MEP_INSN_CPMOVHLA1_W_P1, MEP_INSN_CPACSUMA1_P1
+ , MEP_INSN_CPACCPA1_P1, MEP_INSN_CPACSWP_P1, MEP_INSN_CPSRLA1_P1, MEP_INSN_CPSRAA1_P1
+ , MEP_INSN_CPSLLA1_P1, MEP_INSN_CPSRLIA1_1_P1, MEP_INSN_CPSRAIA1_1_P1, MEP_INSN_CPSLLIA1_1_P1
+ , MEP_INSN_CPFMULIA1S0U_B_P1, MEP_INSN_CPFMULIA1S0_B_P1, MEP_INSN_CPFMULIUA1S0_H_P1, MEP_INSN_CPFMULILA1S0_H_P1
+ , MEP_INSN_CPFMADIA1S0U_B_P1, MEP_INSN_CPFMADIA1S0_B_P1, MEP_INSN_CPFMADIUA1S0_H_P1, MEP_INSN_CPFMADILA1S0_H_P1
+ , MEP_INSN_CPFMULIA1S1U_B_P1, MEP_INSN_CPFMULIA1S1_B_P1, MEP_INSN_CPFMULIUA1S1_H_P1, MEP_INSN_CPFMULILA1S1_H_P1
+ , MEP_INSN_CPFMADIA1S1U_B_P1, MEP_INSN_CPFMADIA1S1_B_P1, MEP_INSN_CPFMADIUA1S1_H_P1, MEP_INSN_CPFMADILA1S1_H_P1
+ , MEP_INSN_CPAMULIA1U_B_P1, MEP_INSN_CPAMULIA1_B_P1, MEP_INSN_CPAMULIUA1_H_P1, MEP_INSN_CPAMULILA1_H_P1
+ , MEP_INSN_CPAMADIA1U_B_P1, MEP_INSN_CPAMADIA1_B_P1, MEP_INSN_CPAMADIUA1_H_P1, MEP_INSN_CPAMADILA1_H_P1
+ , MEP_INSN_CPFMULIA1U_B_P1, MEP_INSN_CPFMULIA1_B_P1, MEP_INSN_CPFMULIUA1_H_P1, MEP_INSN_CPFMULILA1_H_P1
+ , MEP_INSN_CPFMADIA1U_B_P1, MEP_INSN_CPFMADIA1_B_P1, MEP_INSN_CPFMADIUA1_H_P1, MEP_INSN_CPFMADILA1_H_P1
+ , MEP_INSN_CPSSQA1U_B_P1, MEP_INSN_CPSSQA1_B_P1, MEP_INSN_CPSSDA1U_B_P1, MEP_INSN_CPSSDA1_B_P1
+ , MEP_INSN_CPMULA1U_B_P1, MEP_INSN_CPMULA1_B_P1, MEP_INSN_CPMULUA1_H_P1, MEP_INSN_CPMULLA1_H_P1
+ , MEP_INSN_CPMULUA1U_W_P1, MEP_INSN_CPMULLA1U_W_P1, MEP_INSN_CPMULUA1_W_P1, MEP_INSN_CPMULLA1_W_P1
+ , MEP_INSN_CPMADA1U_B_P1, MEP_INSN_CPMADA1_B_P1, MEP_INSN_CPMADUA1_H_P1, MEP_INSN_CPMADLA1_H_P1
+ , MEP_INSN_CPMADUA1U_W_P1, MEP_INSN_CPMADLA1U_W_P1, MEP_INSN_CPMADUA1_W_P1, MEP_INSN_CPMADLA1_W_P1
+ , MEP_INSN_CPMSBUA1_H_P1, MEP_INSN_CPMSBLA1_H_P1, MEP_INSN_CPMSBUA1U_W_P1, MEP_INSN_CPMSBLA1U_W_P1
+ , MEP_INSN_CPMSBUA1_W_P1, MEP_INSN_CPMSBLA1_W_P1, MEP_INSN_CPSMADUA1_H_P1, MEP_INSN_CPSMADLA1_H_P1
+ , MEP_INSN_CPSMADUA1_W_P1, MEP_INSN_CPSMADLA1_W_P1, MEP_INSN_CPSMSBUA1_H_P1, MEP_INSN_CPSMSBLA1_H_P1
+ , MEP_INSN_CPSMSBUA1_W_P1, MEP_INSN_CPSMSBLA1_W_P1, MEP_INSN_CPMULSLUA1_H_P1, MEP_INSN_CPMULSLLA1_H_P1
+ , MEP_INSN_CPMULSLUA1_W_P1, MEP_INSN_CPMULSLLA1_W_P1, MEP_INSN_CPSMADSLUA1_H_P1, MEP_INSN_CPSMADSLLA1_H_P1
+ , MEP_INSN_CPSMADSLUA1_W_P1, MEP_INSN_CPSMADSLLA1_W_P1, MEP_INSN_CPSMSBSLUA1_H_P1, MEP_INSN_CPSMSBSLLA1_H_P1
+ , MEP_INSN_CPSMSBSLUA1_W_P1, MEP_INSN_CPSMSBSLLA1_W_P1
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */