VS_OPCODE_URB_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
- VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */,
0, 0);
- case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
- if (devinfo->gen >= 8)
- return calculate_desc(info, unit_fpu, 12 /* XXX */, 0, 0,
- 4 /* XXX */, 0,
- 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
- 0, 0);
- else
- abort();
-
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
case TCS_OPCODE_GET_INSTANCE_ID:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
return "pull_constant_load_gen7";
- case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
- return "set_simd4x2_header_gen9";
-
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
return "unpack_flags_simd4x2";
case VEC4_OPCODE_SET_HIGH_32BIT:
case VS_OPCODE_PULL_CONSTANT_LOAD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
- case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
}
static void
-generate_set_simd4x2_header_gen9(struct brw_codegen *p,
- vec4_instruction *,
- struct brw_reg dst)
-{
- brw_push_insn_state(p);
- brw_set_default_mask_control(p, BRW_MASK_DISABLE);
-
- brw_set_default_exec_size(p, BRW_EXECUTE_8);
- brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
-
- brw_set_default_access_mode(p, BRW_ALIGN_1);
- brw_MOV(p, get_element_ud(dst, 2),
- brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
-
- brw_pop_insn_state(p);
-}
-
-static void
generate_mov_indirect(struct brw_codegen *p,
vec4_instruction *,
struct brw_reg dst, struct brw_reg reg,
send_count++;
break;
- case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
- generate_set_simd4x2_header_gen9(p, inst, dst);
- break;
-
case GS_OPCODE_URB_WRITE:
generate_gs_urb_write(p, inst);
send_count++;
/* The message header is necessary for:
* - Gen4 (always)
- * - Gen9+ for selecting SIMD4x2
* - Texel offsets
* - Gather channel selection
* - Sampler indices too large to fit in a 4-bit value.