arm64: tegra: Enable PCIe slots in P3737-0000 board

Enable PCIe controller nodes to enable respective PCIe slots on
P3737-0000 board. Following is the ownership of slots by different
PCIe controllers.
Controller-1 : On-board Broadcom WiFi controller
Controller-4 : M.2 Key-M slot
Controller-5 : CEM form-factor x8 slot

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index 02a10bb..dc11a4f 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -2111,4 +2111,55 @@
 
                label = "NVIDIA Jetson AGX Orin APE";
        };
+
+       pcie@14100000 {
+               status = "okay";
+
+               vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+               phys = <&p2u_hsio_3>;
+               phy-names = "p2u-0";
+       };
+
+       pcie@14160000 {
+               status = "okay";
+
+               vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+               phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+                      <&p2u_hsio_7>;
+               phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+       };
+
+       pcie@141a0000 {
+               status = "okay";
+
+               vddio-pex-ctl-supply = <&vdd_1v8_ls>;
+               vpcie3v3-supply = <&vdd_3v3_pcie>;
+               vpcie12v-supply = <&vdd_12v_pcie>;
+
+               phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+                      <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+                      <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+               phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+                           "p2u-5", "p2u-6", "p2u-7";
+       };
+
+       pcie-ep@141a0000 {
+               status = "disabled";
+
+               vddio-pex-ctl-supply = <&vdd_1v8_ls>;
+
+               reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
+
+               nvidia,refclk-select-gpios = <&gpio_aon
+                                             TEGRA234_AON_GPIO(AA, 4)
+                                             GPIO_ACTIVE_HIGH>;
+
+               phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+                      <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+                      <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+               phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+                           "p2u-5", "p2u-6", "p2u-7";
+       };
 };