gas/config/tc-arm.c: Fix parsing of NEON load/store element sizes.
authorWill Newton <willnewton@sourceware.org>
Mon, 16 Sep 2013 09:34:30 +0000 (09:34 +0000)
committerWill Newton <willnewton@sourceware.org>
Mon, 16 Sep 2013 09:34:30 +0000 (09:34 +0000)
The existing code would accept VLD2.64 and similar undefined
instructions.

gas/ChangeLog:

2013-09-16  Will Newton  <will.newton@linaro.org>

* config/tc-arm.c (do_neon_ld_st_interleave): Add constraint
disallowing element size 64 with interleave other than 1.

gas/testsuite/ChangeLog:

2013-09-16  Will Newton  <will.newton@linaro.org>

* gas/arm/neon-ldst-es.d: Add VLD1.64 instructions.
* gas/arm/neon-ldst-es.s: Likewise.
* testsuite/gas/arm/neon-ldst-es-bad.d: New file.
* testsuite/gas/arm/neon-ldst-es-bad.l: Likewise.
* testsuite/gas/arm/neon-ldst-es-bad.s: Likewise.

gas/ChangeLog
gas/config/tc-arm.c
gas/testsuite/ChangeLog
gas/testsuite/gas/arm/neon-ldst-es-bad.d [new file with mode: 0644]
gas/testsuite/gas/arm/neon-ldst-es-bad.l [new file with mode: 0644]
gas/testsuite/gas/arm/neon-ldst-es-bad.s [new file with mode: 0644]
gas/testsuite/gas/arm/neon-ldst-es.d
gas/testsuite/gas/arm/neon-ldst-es.s

index 8434721..8177107 100644 (file)
@@ -1,3 +1,8 @@
+2013-09-16  Will Newton  <will.newton@linaro.org>
+
+       * config/tc-arm.c (do_neon_ld_st_interleave): Add constraint
+       disallowing element size 64 with interleave other than 1.
+
 2013-09-12  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 
        * config/tc-mips.c (match_insn): Set error when $31 is used for
index 8c405a8..9c8211d 100644 (file)
@@ -15783,6 +15783,8 @@ do_neon_ld_st_interleave (void)
   typebits = typetable[idx];
 
   constraint (typebits == -1, _("bad list type for instruction"));
+  constraint (((inst.instruction >> 8) & 3) && et.size == 64,
+             _("bad element type for instruction"));
 
   inst.instruction &= ~0xf00;
   inst.instruction |= typebits << 8;
index ac33815..f2d5d56 100644 (file)
@@ -1,3 +1,11 @@
+2013-09-16  Will Newton  <will.newton@linaro.org>
+
+       * gas/arm/neon-ldst-es.d: Add VLD1.64 instructions.
+       * gas/arm/neon-ldst-es.s: Likewise.
+       * testsuite/gas/arm/neon-ldst-es-bad.d: New file.
+       * testsuite/gas/arm/neon-ldst-es-bad.l: Likewise.
+       * testsuite/gas/arm/neon-ldst-es-bad.s: Likewise.
+
 2013-09-12  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 
        * gas/mips/bltzal.s: New file.
diff --git a/gas/testsuite/gas/arm/neon-ldst-es-bad.d b/gas/testsuite/gas/arm/neon-ldst-es-bad.d
new file mode 100644 (file)
index 0000000..576ee7a
--- /dev/null
@@ -0,0 +1,3 @@
+# name: Bad element size combinations in Neon load/store instructions
+# as: -mfpu=neon
+# error-output: neon-ldst-es-bad.l
diff --git a/gas/testsuite/gas/arm/neon-ldst-es-bad.l b/gas/testsuite/gas/arm/neon-ldst-es-bad.l
new file mode 100644 (file)
index 0000000..b0c854e
--- /dev/null
@@ -0,0 +1,12 @@
+[^:]*: Assembler messages:
+[^:]*:2: Error: bad type in Neon instruction -- `vld1\.64 {d0\[1\]},\[r0\]'
+[^:]*:3: Error: bad type in Neon instruction -- `vld1\.64 {d0\[\]},\[r0\]'
+[^:]*:4: Error: bad type in Neon instruction -- `vld2\.64 {d0\[1\]},\[r0\]'
+[^:]*:5: Error: bad type in Neon instruction -- `vld2\.64 {d0\[\]},\[r0\]'
+[^:]*:6: Error: bad element type for instruction -- `vld2\.64 {d0-d1},\[r0\]'
+[^:]*:7: Error: bad type in Neon instruction -- `vld3\.64 {d0\[1\]},\[r0\]'
+[^:]*:8: Error: bad type in Neon instruction -- `vld3\.64 {d0\[\]},\[r0\]'
+[^:]*:9: Error: bad element type for instruction -- `vld3\.64 {d0-d2},\[r0\]'
+[^:]*:10: Error: bad type in Neon instruction -- `vld4\.64 {d0\[1\]},\[r0\]'
+[^:]*:11: Error: bad type in Neon instruction -- `vld4\.64 {d0\[\]},\[r0\]'
+[^:]*:12: Error: bad element type for instruction -- `vld4\.64 {d0-d3},\[r0\]'
diff --git a/gas/testsuite/gas/arm/neon-ldst-es-bad.s b/gas/testsuite/gas/arm/neon-ldst-es-bad.s
new file mode 100644 (file)
index 0000000..f7e335e
--- /dev/null
@@ -0,0 +1,12 @@
+       .text
+       vld1.64 {d0[1]}, [r0]
+       vld1.64 {d0[]}, [r0]
+       vld2.64 {d0[1]}, [r0]
+       vld2.64 {d0[]}, [r0]
+       vld2.64 {d0-d1}, [r0]
+       vld3.64 {d0[1]}, [r0]
+       vld3.64 {d0[]}, [r0]
+       vld3.64 {d0-d2}, [r0]
+       vld4.64 {d0[1]}, [r0]
+       vld4.64 {d0[]}, [r0]
+       vld4.64 {d0-d3}, [r0]
index 6c22c69..e9c0734 100644 (file)
@@ -56,3 +56,5 @@ Disassembly of section \.text:
 0[0-9a-f]+ <[^>]+> f427208f    vld4\.32        {d2-d5}, \[r7\]
 0[0-9a-f]+ <[^>]+> f467c08f    vld4\.32        {d28-d31}, \[r7\]
 0[0-9a-f]+ <[^>]+> f4a21c83    vld1\.32        {d1\[\]}, \[r2\], r3
+0[0-9a-f]+ <[^>]+> f42007cf    vld1\.64        {d0}, \[r0\]
+0[0-9a-f]+ <[^>]+> f42002cf    vld1\.64        {d0-d3}, \[r0\]
index 79f4b0c..cb93f06 100644 (file)
@@ -60,3 +60,6 @@
 
        @ PR 14987 and 14887: Allow for whitespace in the instruction.
        vld1.32 { d1 [ ] } , [ r2 ] , r3
+
+       vld1.64 {d0}, [r0]
+       vld1.64 {d0-d3}, [r0]