[PPC] Fix the scheduling of CR logicals on the P7

CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).

This will matter when, in an upcoming commit, we start generating these
instructions.

llvm-svn: 198359

diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 0c07fd3..37c85b3 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -128,6 +128,7 @@ bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
   default:
     // All multi-slot instructions must come first.
     return NSlots > 1;
+  case PPC::Sched::IIC_BrCR: // cr logicals
   case PPC::Sched::IIC_SprMFCR:
   case PPC::Sched::IIC_SprMFCRF:
   case PPC::Sched::IIC_SprMTSPR:

diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
index 958bc90..a3670a5 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
@@ -137,8 +137,8 @@ def P7Itineraries : ProcessorItineraries<
   InstrItinData<IIC_BrB         , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
                                    InstrStage<1, [P7_BRU]>],
                                   [3, 1, 1]>,
-  InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
-                                   InstrStage<1, [P7_BRU]>],
+  InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU1], 0>,
+                                   InstrStage<1, [P7_CRU]>],
                                   [3, 1, 1]>,
   InstrItinData<IIC_BrMCR       , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
                                    InstrStage<1, [P7_BRU]>],